DRAM Memory Controller ECC Read Modify Write Optimization
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Solution Overview
Problem
In semiconductor memories like DRAMs, ECC processing for data of sizes smaller than the predetermined data length results in longer processing times due to the need for read modify write operations, which can be slower than masked writes used in systems without ECC processing.
Innovation Solution
Implementing a memory controller that performs read modify write processing within the DRAM, allowing for efficient handling of data sizes smaller than the ECC processing unit by executing read modify write operations internally, thereby matching or exceeding the performance of systems without ECC processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC processing is implemented in DRAM, then data reliability is improved, but writing performance for small data sizes deteriorates
Solution Approach 1:
The invention segments the write operation into two independent paths: a fast masked write path for small data sizes (without ECC) and a reliable ECC write path for full-sized data. The memory controller selectively routes small writes to bypass ECC processing, while full writes undergo ECC processing. This segmentation resolves the contradiction by allowing each path to optimize for its specific requirements.
Solution Approach 2:
The memory controller dynamically adjusts the write path based on data size. For small data sizes, it uses masked write without ECC; for full data sizes, it uses read-modify-write with ECC. This dynamic adaptation allows the system to achieve both high performance for small writes and high reliability for full writes, resolving the performance-reliability tradeoff.
2Reliability
If read modify write processing is executed for small data, then data reliability is maintained, but processing time increases
Solution Approach 1:
The invention extracts the ECC processing step from the write operation for small data sizes. By using masked write, the small data writes bypass the read-modify-write cycle entirely, eliminating the time-consuming ECC calculation and memory access steps while still maintaining reliability through the fast write path.
Solution Approach 2:
For small data sizes, the system applies partial action by performing only the necessary masked write operation without the full read-modify-write ECC process. This partial execution of the write function achieves sufficient reliability for small data while significantly reducing processing time.
3Productivity
If masked write is used for small data, then writing performance is improved, but error correction capability is lost
Solution Approach 1:
The invention applies local quality by providing different write characteristics to different data sizes: small data gets fast masked write without ECC, while full data gets reliable read-modify-write with ECC. Each data size category receives the appropriate quality level for its requirements, optimizing both performance and reliability where needed.
Data Source
AI summary
An information processing apparatus including a memory and a memory controller writing data to the memory in response to a write for writing the data to the memory, in which the memory executes error correction processing for each data of a predetermined data length, and the memory controller executes, in place of the memory, read modify write processing in a case where a data length of the data related to the write instruction is smaller than the predetermined data length.