Distributed DrMOS Gate Drive for Uniform Switching and Low Inductance

The gate contact pad is divided into multiple smaller contact regions distributed across the gate structure. Instead of using a single large pad, the patent implements multiple gate contacts that are distributed across the gate, allowing current to flow through multiple paths. This segmentation reduces the area occupied by gate contacts while maintaining reliable electrical connection through distributed contact points.

The patent extracts and eliminates the bond wire connection method from the package structure. By transitioning to a wafer-level integrated approach where chips are connected through the substrate plane rather than through air-based bond wires, the harmful parasitic inductance inherent to bond wires is removed. The connection is reimagined without the intermediate bond wire element that causes inductance.

The patent merges the mechanical support function into the wafer substrate itself. Instead of using separate lead frames and clips as additional structural elements, the substrate is designed to provide both electrical connection and mechanical support functions. The chips are mounted directly on the substrate which provides inherent mechanical strength, eliminating the need for separate support structures and reducing overall device size.

The gate contact is segmented into multiple distributed contact points across the gate structure. This segmentation creates multiple parallel current paths that distribute the gate current uniformly across the gate width. The distributed gate contacts ensure uniform gate impedance and uniform electric field distribution, which enables uniform switching behavior across the entire device while maintaining manageable connection complexity through standardized contact patterns.