DROIC Modulated Light Rejection via Count Enable
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Solution Overview
Problem
Conventional image capturing devices face challenges in maintaining image quality when exposed to high intensity modulated or pulsed light sources, leading to saturation and false digital counts that degrade image quality and post-processing algorithms.
Innovation Solution
A digital pixel circuit with a 'count enable' feature, where the Digital Readout Integrated Circuit (DROIC) counts electric charge reset events only when the count enable signal is true, and the frequency and duty cycle of this signal are adjusted to match and oppose the external modulated light source, minimizing its impact on imaging information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional image capturing devices use traditional well capacitor integration, then the device structure remains simple, but the device saturates and produces false digital counts when exposed to high intensity modulated light sources
Solution Approach 1:
The patent applies dynamics by making the counting function conditional rather than static. The DROIC dynamically enables or disables reset event counting based on the state of a count enable signal, allowing the system to adapt its behavior to different lighting conditions and prevent saturation from modulated light sources
Solution Approach 2:
The patent uses periodic action by synchronizing the count enable signal with the frequency and duty cycle of external modulated light sources. By periodically enabling counting only during intervals when modulated light is not present, the system eliminates false digital counts while maintaining simplicity
2Reliability
If the DROIC continuously counts all reset events, then the counting is simple, but modulated light causes false digital counts that degrade image quality
Solution Approach 1:
The patent extracts the harmful effect of modulated light by selectively excluding reset events that occur during modulated light intervals from the digital count. The count enable signal acts as a filter that takes out only the problematic counting periods, allowing accurate digital counts to be generated from genuine scene light while rejecting false counts from modulated sources
Solution Approach 2:
The system uses feedback by monitoring the count enable signal state and adjusting the counting behavior accordingly. The DROIC receives feedback about when modulated light is present and modifies its counting operation in real-time, enabling accurate differentiation between genuine photo-charge accumulation and modulated light interference
3Manufacturing precision
If pixel size is reduced to increase resolution, then the image detail improves, but the well capacitor capacity decreases leading to reduced charge storage ability
Solution Approach 1:
The patent transitions from spatial dimension to temporal dimension by using time-based multiplexing. Instead of increasing capacitor size spatially, the system achieves increased effective capacity by utilizing multiple integration intervals over time, allowing small capacitors in reduced-size pixels to accumulate sufficient charge through repeated counting cycles
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the impact of modulated light on image quality by accurately counting reset events, preventing saturation and improving image clarity, even in the presence of high-intensity pulsed light sources.
Implementation Method 1
a circuit or imager within a unit cell to accumulate charge from a photo-diode, the charge corresponding to the flux of light of various wavelengths incident on the photo-diode
Data Source
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AI summary
According to one aspect, embodiments herein provide a digital pixel circuit comprising a detector configured to discharge a well capacitor when voltage across the well capacitor exceeds a threshold, a DROIC configured, in a first mode, to increment a reset counter when the well capacitor is discharged, and in a second mode, to ignore the discharging of the well capacitor, and a processing unit configured to monitor a count rate of the DROIC, transmit a signal at a first level when the count rate is less than a threshold, and transmit a signal at a second level when the count rate is greater than the threshold, wherein, the DROIC is further configured, in response to receiving the signal at the first level, to operate in the first mode, and in response to receiving the signal at the second level, to operate in the second mode.