Power Regulation Circuit With Droop Detection and Clock Slowdown
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Solution Overview
Problem
Power regulation circuits face challenges in mitigating droops in power source voltage caused by impedance changes, particularly the second droop which occurs at higher frequencies, leading to voltage drops that affect processing core performance.
Innovation Solution
A power regulation circuit that includes a first droop detector with a high pass filter and a second droop detector with a bandpass filter, generating detection signals to trigger a frequency slowdown signal for a digitally controlled oscillator to adjust the clock signal frequency, thereby mitigating or eliminating both the first and second droops in the power source voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are populated on power rails or more copper layers are added to reduce impedance, then second droop magnitude is reduced, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent implements a feedback mechanism where droop detection circuits continuously monitor the power source voltage for droop events. When droop is detected, the system generates a slowdown signal that feeds back to the digitally controlled oscillator to reduce clock frequency, thereby preventing further voltage drops without requiring additional hardware components on the power rails.
Solution Approach 2:
The patent replaces the physical/mechanical approach of adding capacitors and copper layers with an electronic/software-based solution. Instead of modifying the physical power rail structure, the system uses electronic detection and control signals to manage voltage stability, substituting hardware complexity with electronic control logic.
2Reliability
If clock signal frequency is reduced to mitigate droop, then power source voltage stability is improved, but processing core performance decreases
Solution Approach 1:
The patent implements dynamic frequency adjustment where the clock signal frequency is not fixed but varies based on real-time power source voltage conditions. The digitally controlled oscillator dynamically changes frequency in response to droop detection, allowing the system to optimize between voltage stability and processing performance based on current operating conditions.
Solution Approach 2:
The patent changes the operating parameters of the processing system by adjusting the clock frequency as a variable parameter rather than a fixed value. This allows the system to adapt its performance characteristics to match power availability, changing the frequency parameter to maintain voltage stability while minimizing performance impact.
3Reliability
If droop detection and frequency slowdown control are implemented, then both first and second droops are mitigated, but device complexity increases
Solution Approach 1:
The patent segments the droop mitigation function into distinct modular components: droop detection circuits for monitoring voltage, droop detection logic for analyzing detected conditions, and a digitally controlled oscillator for frequency adjustment. This segmentation allows each component to perform its specific function independently, making the overall complex system manageable and maintainable.
Data Source
AI summary
Embodiments of a power regulation circuit that ameliorates a first and second droop in a power source voltage that powers a processing core are disclosed. The power regulation circuit includes a first droop detector, a second droop detector and a frequency slowdown detection circuit. The first droop detector generates a first droop detection signal in a first detection state in response to detecting a first droop in the power source voltage. The second droop detector generates a second droop detection signal in a second detection state in response to detecting a second droop in the power source voltage. The frequency slowdown detection circuit to generate a frequency slowdown signal in a slowdown state in response to at least one of the first droop detection signal being in the first detection state and the second droop detection signal being in the second detection state.