Multi-Phase Drowsy Clock Generation for Precise Low-Speed IC Testing
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Solution Overview
Problem
Conventional integrated circuit testing using low-frequency test signals is hindered by external noise entering the internal circuit, leading to imprecise performance testing due to phase changes in clock signals.
Innovation Solution
An integrated circuit device that generates drowsy clock signals with a constant phase difference, using a phase synchronizer and feedback unit to divide and align frequencies, allowing for precise testing at lower speeds without requiring high-speed test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If low-frequency clock signals are applied to the internal circuit via pads, then testing can be performed using less expensive low-frequency test equipment, but external noise enters the internal circuit causing phase changes and imprecise testing
Solution Approach 1:
A phase synchronizer is introduced as an intermediary component that receives the low-frequency clock signal from the test equipment and generates synchronized clock signals for the internal circuit. This mediator ensures that the clock signals maintain precise phase relationships while still using low-frequency test equipment, thereby achieving both cost savings and testing precision.
Solution Approach 2:
The patent implements a feedback mechanism where the phase synchronizer continuously monitors and adjusts the phase of clock signals to maintain synchronization. This feedback loop compensates for any phase deviations caused by external noise, ensuring precise testing while using low-frequency test equipment.
2Measurement precision
If high-frequency test equipment is used to generate high-frequency test signals, then testing precision is improved, but the equipment becomes more expensive and harder to upgrade
Solution Approach 1:
The patent changes the frequency parameter of the clock signals generated by the test equipment, using low-frequency signals instead of high-frequency signals. By introducing a phase synchronizer that can process low-frequency signals and generate precise clock outputs, the system achieves testing precision previously only available with high-frequency equipment, thereby reducing test equipment costs.
3Speed
If low-frequency clock signals are used for testing, then testing at lower speeds is enabled, but phase changes due to external noise reduce testing accuracy
Solution Approach 1:
The phase synchronizer acts as an intermediary between the low-frequency clock signal source and the internal circuit. It receives the low-frequency signal and generates multiple synchronized clock signals with precise phase relationships, enabling both low-speed testing and high precision by compensating for noise-induced phase changes.
Solution Approach 2:
The phase synchronizer performs preliminary synchronization of the clock signals before they are applied to the internal circuit. By pre-aligning the phases and generating clean, synchronized clock signals in advance, the system enables accurate low-speed testing without the phase distortion problems that would otherwise occur with low-frequency signals.
Data Source
AI summary
An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having different phases in response to an external clock signal and a drowsy clock signal output unit configured to divide frequencies of the plurality of clock signals by a first factor, align the frequency-divided clock signals so that each consecutive clock signal has a constant phase difference relative to a phase difference of a preceding clock signal, and output the drowsy clock signals having lower frequencies and different phases. The integrated circuit device also includes a feedback unit configured to divide frequency of a clock signal with a phase angle of 0 output by the phase synchronizer by the first factor and output the frequency-divided clock signal having a phase angle of 0 degrees to an input port of the phase synchronizer.