Dynamically Reconfigurable Processor Value Persistence via Compiler-Managed Storage
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Solution Overview
Problem
Prior art dynamically reconfigurable processors face challenges in efficiently persisting values across instruction execution cycles, leading to conflicts in assigning hardware elements for value storage, which affects the correct execution and reconfiguration of instructions.
Innovation Solution
A method and compiler that manage value storage and positioning within dynamically reconfigurable processors by persisting values across instruction execution cycles, using a software model to compile software code that optimally handles value storage and reconfiguration, and employing techniques like array links and register links to resolve conflicts and ensure correct value access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If values are persisted across instruction execution cycles in dynamically reconfigurable processors, then correct data access and processing is ensured, but conflicts in hardware element assignment occur
Solution Approach 1:
The patent segments the hardware resources into separate value storage elements and iterator components. By dividing the storage function into dedicated elements that can be independently managed, the system avoids conflicts in hardware element assignment while ensuring correct value persistence across instruction cycles.
Solution Approach 2:
The patent introduces iterator components as intermediaries between the value storage elements and the instruction execution units. These iterators manage the assignment and access of stored values, preventing direct conflicts in hardware element assignment while maintaining reliable data access throughout the reconfiguration process.
2Productivity
If hardware elements are reused across multiple instructions, then device efficiency is improved, but value persistence conflicts arise
Solution Approach 1:
The patent implements dynamic value storage elements that can be reconfigured and reassigned based on the current instruction's needs. This dynamic approach allows hardware elements to be efficiently reused across multiple instructions while maintaining proper value persistence through controlled reconfiguration sequences managed by the iterator components.
3Adaptability or versatility
If reconfiguration occurs between instructions, then adaptability is improved, but value access conflicts occur
Solution Approach 1:
The patent performs preliminary actions by pre-configuring and storing values in dedicated storage elements before instruction execution begins. The iterator components prepare the value access paths in advance, ensuring that reconfiguration between instructions does not cause value access conflicts, as the necessary values are already positioned and protected for retrieval.
Data Source
AI summary
A method and system for enabling persistence of a value by a dynamically reconfigurable processor (“DRP”) from the time of execution of an earlier executed instruction to a time of later executed instruction. The value may represent a constant a variable value of a software program. The value may be read from or written into a memory circuit, a DRP logic element, an iterator of a DRP logic element, or other value storing element or aspect of the DRP. The value may be maintained in a single logic element through the duration of one or more instruction execution cycles, or alternatively or additionally, the value may be transferred between or among one or more value storage hardware elements. The persistence of the value and transfer of the value within, into and/or out of the DRP enables later access of the value by, and/or positioning the value within, the DRP.