DRAM Buried Gate Shallow Trench Isolation Height

Solution Overview

Problem

Current DRAM units with buried gate structures face limitations in fabrication, leading to performance and reliability issues due to limited capabilities, particularly in reducing capacitor leakage and addressing the row hammer effect caused by electronic interference between adjacent gate lines.

Innovation Solution

The method involves forming shallow trench isolation (STI) with a top portion and a bottom portion, where the top surface of the top portion is even with or higher than the bottom surface of adjacent trenches, to increase the overall height of the STI before forming gate structures, ensuring that the gate structures are at least even with or higher than adjacent gate structures, thereby reducing the row hammer effect.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional DRAM units with buried gate structures are used, then carrier channel length is extended to reduce capacitor leakage, but electronic interference between adjacent gate lines causes row hammer effect

Engineering Contradiction:

Improvecapacitor leakage reductionVSAvoidelectronic interference between gate lines

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The isolation structure is segmented into two distinct parts: a first isolation layer filling the first trench and a second isolation layer filling the second trench. This segmentation allows each layer to be optimized independently, with the first layer providing baseline isolation and the second layer providing enhanced protection against electronic interference, thereby resolving the row hammer effect while maintaining leakage reduction.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the isolation structure are assigned different properties: the first isolation layer uses a first dielectric material with specific electrical characteristics, while the second isolation layer uses a second dielectric material with superior electrical isolation properties. This local quality differentiation ensures that the critical region between adjacent gate lines receives enhanced isolation to prevent electronic interference, while maintaining overall device performance.

Inventive Principle:

Principle #3Local quality

2Productivity

If higher integration and density are achieved through miniaturization, then DRAM unit size is reduced, but fabrication capability becomes limited leading to performance degradation

Engineering Contradiction:

Improveintegration and densityVSAvoidfabrication capability

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The isolation structure extends in the vertical dimension with two stacked isolation layers, rather than relying solely on horizontal planar isolation. This dimensional approach allows enhanced electrical isolation between adjacent gate lines without increasing the lateral footprint of the DRAM unit, thereby maintaining high integration and density while improving fabrication robustness and device performance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If single-layer isolation structure is used, then fabrication process is simpler, but electronic interference between adjacent gate structures cannot be effectively reduced

Engineering Contradiction:

Improveisolation structure fabricationVSAvoidrow hammer effect

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The isolation structure is segmented into two distinct parts: a first isolation layer filling the first trench and a second isolation layer filling the second trench. This segmentation allows each layer to be optimized independently, with the first layer providing baseline isolation and the second layer providing enhanced protection against electronic interference, thereby resolving the row hammer effect while maintaining manufacturing feasibility through systematic process integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The isolation structure employs composite dielectric materials with different electrical properties: the first isolation layer uses a first dielectric material and the second isolation layer uses a second dielectric material with superior electrical isolation characteristics. This composite approach effectively reduces electronic interference between adjacent gate structures while maintaining a fabrication process that integrates seamlessly with existing manufacturing capabilities.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS10396073B2Semiconductor device and method for fabricating the same

Publication Date: 2019.08.27 UNITED MICROELECTRONICS CORP

AI summary

A method for fabricating semiconductor device includes the steps of first forming a first trench and a second trench in a substrate and then forming a shallow trench isolation (STI) in the first trench, in which the STI comprises a top portion and a bottom portion and a top surface of the top portion is even with or higher than a bottom surface of the second trench. Next, a conductive layer is formed in the first trench and the second trench to form a first gate structure and a second gate structure.