DRAM Capacitor Etching via Segmented Masking to Prevent Punch-Through

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Solution Overview

Problem

The punch-through phenomenon during the etching process to form metal contacts in DRAM devices increases contact resistance due to reduced contact area between the final metal interconnection line and the top electrode of the capacitor.

Innovation Solution

A method involving multiple etch steps with etch gases of high selectivity to specific layers is employed to prevent punch-through, ensuring the top electrode is not damaged and maintaining a larger contact area, including the use of amorphous silicon and polysilicon layers with specific etch gases to control the etching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single etching process is used to form metal contacts exposing both the plate electrode and bit line, then the etching process can complete both exposures, but the punch-through phenomenon occurs in the plate electrode reducing contact area

Engineering Contradiction:
Improveetching process efficiencyVSAvoidcontact area precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent divides the single etching process into multiple sequential etching steps. The first etching step exposes the bit line while the second etching step exposes the plate electrode. This segmentation prevents the punch-through phenomenon by controlling the etching depth and timing for each target, ensuring precise contact area formation without damaging the plate electrode.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If the etching process continues to expose the bit line, then the bit line exposure is achieved, but the contact area between metal contact and plate electrode is reduced due to punch-through

Engineering Contradiction:
Improvebit line exposureVSAvoidcontact resistance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent performs the bit line exposure in a preliminary etching step before the plate electrode exposure step. By completing the bit line exposure first and then proceeding to expose the plate electrode in a controlled second step, the method ensures that the plate electrode is not subjected to excessive etching that would cause punch-through and increase contact resistance.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If identical etch gas is used throughout the mask etching process, then the etching process is simple, but the punch-through phenomenon is produced in the plate electrode

Engineering Contradiction:
Improveetching process complexityVSAvoidplate electrode integrity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent changes the etching parameters by using different etch gases for different etching steps. The first etching step uses an etch gas mixture optimized for exposing the bit line, while the second etching step uses a different etch gas mixture optimized for exposing the plate electrode without causing punch-through. This parameter change enables precise control over the etching process while maintaining plate electrode integrity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance between the metal contact and the top electrode, preventing punch-through and enhancing the yield of semiconductor devices by maintaining a larger contact area and preventing damage to the top electrode.

Implementation Method 1

An etching process using a mask is performed to form a plurality of metal contacts M1C exposing predetermined upper portions of the plate electrode PLATE and the bit line BL

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS7396772B2Method for fabricating semiconductor device having capacitor
Publication Date: 2008.07.08 MOSAID TECH
  • US7396772B2 patent drawing
  • US7396772B2 patent drawing
  • US7396772B2 patent drawing

AI summary

A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.