DRAM Capacitor Integration Among Metal Interconnects
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Solution Overview
Problem
Stacked DRAM solutions face contamination issues due to copper interconnect metal, which complicates the integration of capacitors and reduces capacitance, necessitating costly diffusion barrier layers that become difficult to implement with scaling.
Innovation Solution
The technique involves removing copper interconnect metal using a selective wet etch process before capacitor formation, eliminating contamination and allowing for increased capacitor height and capacitance without the need for diffusion barriers, and using conformal atomic layer deposition for the bottom electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitors are integrated above interconnect metals in stacked configuration, then three-dimensional integration density is improved, but metal contamination of high-k dielectric occurs and diffusion barrier layers are required
Solution Approach 1:
The patent removes the metal landing pad structure that would normally be present in stacked DRAM configurations. By extracting this metal component, the invention eliminates the contamination source while maintaining the three-dimensional integration architecture, allowing capacitors to be formed directly on the substrate without metal interference
Solution Approach 2:
The patent performs metal removal prior to capacitor formation. By eliminating the metal landing pad before depositing the high-k dielectric layer, the invention prevents contamination from occurring in the first place, avoiding the need for subsequent barrier layers
2Object-affected harmful factors
If diffusion barrier layers are added to prevent metal contamination, then contamination is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent eliminates the need for diffusion barrier layers by removing the metal landing pad structure. This extraction approach simplifies the device architecture by removing both the contamination source and the protective barrier that would otherwise be required, reducing overall device complexity
Solution Approach 2:
The invention uses a sacrificial metal landing pad that is intentionally removed. This disposable structure serves its purpose during intermediate fabrication steps and is then eliminated, simplifying the final device structure without requiring permanent barrier layers
3Ease of manufacture
If metal landing pad is retained for capacitor formation, then fabrication process is simpler, but metal contaminates high-k dielectric and reduces capacitor performance
Solution Approach 1:
The patent performs metal removal as a preliminary step before capacitor formation. By eliminating the metal landing pad before high-k dielectric deposition, the invention ensures capacitor reliability from the outset without compromising manufacturing simplicity
Solution Approach 2:
The invention uses an intermediary etch stop layer (such as silicon nitride) that facilitates selective metal removal. This mediator enables the fabrication process to proceed smoothly by providing a clear interface for metal elimination while protecting underlying structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contamination, increases capacitor surface area and capacitance, and simplifies the integration process, enabling longer capacitor leakage periods before refresh is required.
Implementation Method 1
uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation
Data Source
AI summary
Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.