DRAM Conductive Line Structure with Vertical Vias
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Solution Overview
Problem
The challenge in fabricating integrated circuitry, such as DRAM, is the occurrence of undesired parasitic capacitance as conductors are made closer together, which adversely impacts design and operation due to increased proximity of components.
Innovation Solution
The solution involves a DRAM construction with recessed access devices and a conductive line structure where elevationally-extending conductive vias directly couple the conductive line structure to individual conductive nodes, utilizing a specific arrangement of insulative and semiconductor materials to minimize parasitic capacitance, including a digitline structure with upper and lower insulative materials and doped or undoped semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductors are placed closer together to increase integration density, then productivity and device miniaturization are improved, but parasitic capacitance increases adversely impacting circuit operation
Solution Approach 1:
The patent transitions from planar conductor arrangement to a three-dimensional structure where conductive vias extend vertically through insulative layers. This vertical dimensionality allows conductors to be closer in the horizontal plane (increasing integration density) while maintaining electrical isolation through the vertical insulative material layers, thereby reducing parasitic capacitance between adjacent conductors.
Solution Approach 2:
Insulative material layers are introduced as intermediary substances between adjacent conductive elements (conductive vias and conductive line structures). These insulative layers act as electrical barriers that prevent direct capacitive coupling between conductors, reducing parasitic capacitance while allowing the conductors to remain in close proximity for high integration density.
2Reliability
If conductive vias are made elevationally-extending to directly couple conductive line structure to conductive nodes, then electrical coupling efficiency is improved, but device complexity increases
Solution Approach 1:
The electrical connection path is segmented into discrete components: conductive nodes, insulative layers, elevationally-extending conductive vias, and conductive line structures. This segmentation allows each component to be independently formed and optimized, improving manufacturing precision and electrical coupling efficiency while managing complexity through modular construction.
Solution Approach 2:
The patent uses vertical (elevational) extending conductive vias to create three-dimensional electrical coupling paths. This vertical dimensionality provides direct electrical connection between conductive nodes and line structures, improving coupling efficiency by eliminating lateral routing through additional conductive layers, while the systematic layering manages construction complexity.
Data Source
AI summary
An integrated circuitry construction comprises a substrate comprising conductive nodes of integrated circuitry. A conductive line structure is above the conductive nodes. Elevationally-extending conductive vias are spaced longitudinally along the conductive line structure. The conductive vias individually directly electrically couple the conductive line structure to individual of the conductive nodes. The conductive line structure comprises conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias. An upper insulative material is directly below the conductive material between the immediately-longitudinally-adjacent conductive vias. Doped or undoped semiconductor material directly is below the upper insulative material between the immediately-longitudinally-adjacent conductive vias. A lower insulative material is directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. Other aspects, including method, are disclosed.