DRAM Refresh Counter with Dummy Bit for Dynamic Timing Control

Solution Overview

Problem

Conventional DRAMs face challenges in adjusting the refresh period to match the actual data retention time of memory cells, leading to insufficient data retention characteristics and excessive current consumption during refresh operations.

Innovation Solution

A semiconductor memory device with a refresh counter that includes n+1 stage counters and a dummy bit, forming an N-ary counter, allows for fine control of refresh timing by using the dummy bit to alternate between refresh and non-refresh periods, thereby adjusting the refresh period to match the data retention time of memory cells and optimizing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If two or more word lines are refreshed simultaneously at every refresh interval, then the refresh period is reduced to half, but the frequency of refresh is likely to be too high so that extra current is consumed

Engineering Contradiction:

Improverefresh periodVSAvoidcurrent consumption

Core Design Contradiction:

Duration of action of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the refresh counter configurable with multiple modes (1:1, 1:2, 1:3, 1:4) that allow dynamic adjustment of the refresh period. This enables the system to adapt the refresh rate to actual data retention requirements, avoiding both insufficient refresh and excessive current consumption. The counter can be reconfigured based on specific memory array characteristics and operational conditions.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of refresh period by introducing a configurable refresh counter that can operate in different modes (1:1, 1:2, 1:3, 1:4). This allows the refresh period to be adjusted from the fixed value to variable values based on actual data retention time requirements, thereby optimizing the balance between data retention and current consumption without consuming extra current through excessive refresh operations.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If one word line is refreshed at every refresh interval, then the refresh period is sufficient for data retention, but the refresh frequency is insufficient for increased storage capacity

Engineering Contradiction:

Improvedata retention characteristicsVSAvoidstorage capacity

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by implementing a configurable refresh counter with multiple modes (1:1, 1:2, 1:3, 1:4) that enable dynamic adjustment of refresh frequency. This allows the system to adapt to increased storage capacity requirements while maintaining adequate data retention, avoiding both insufficient refresh and excessive current consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of refresh period by introducing a configurable refresh counter that can operate in different modes. This enables the refresh period to be adjusted to match actual data retention requirements, allowing the system to handle increased storage capacity while maintaining reliability through appropriate refresh frequency.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If the refresh period is reduced to half by refreshing two word lines simultaneously, then the refresh frequency is doubled, but it is difficult to correspondingly adjust the refresh period to match actual data retention time

Engineering Contradiction:

Improverefresh frequencyVSAvoidadjustment of refresh period

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the refresh counter configurable with multiple modes (1:1, 1:2, 1:3, 1:4) that allow dynamic adjustment of the refresh period. This enables the system to adapt the refresh rate to actual data retention requirements, avoiding both insufficient refresh and excessive current consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of refresh period by introducing a configurable refresh counter that can operate in different modes (1:1, 1:2, 1:3, 1:4). This allows the refresh period to be adjusted from the fixed value to variable values based on actual data retention time requirements, thereby optimizing the balance between data retention and current consumption.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7471586B2Semiconductor memory device which controls refresh of a memory array in normal operation

Publication Date: 2008.12.30 MICRON TECHNOLOGY INC

AI summary

A semiconductor memory device is comprised of a refresh counter for sequentially generating a count value indicating one or more row addresses corresponding to one or more word lines to be refreshed when receiving a refresh request at a predetermined interval in normal operation, in which the refresh counter includes n+1 stage counters assigned to n bits included in the row address and a dummy bit not included in the row address, and a counter portion from the least significant bit to the dummy bit forms an N-ary counter, so as to control whether or not refresh is performed in response to a value of the dummy bit when receiving the refresh request.