DRAM Row Block Timing Adjustment for RC Loading
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Solution Overview
Problem
As the size of memory cell arrays in volatile memory devices, such as DRAM, increases, RC loading on column selection lines and global input/output lines increases, leading to differences in characteristics and affecting read operation characteristics for memory cells at different positions.
Innovation Solution
A semiconductor memory device with a memory cell array divided into row blocks by row block identity bits, where a timing/voltage control circuit adjusts the operation interval and voltage of memory operations based on the distance of row blocks from the column decoder, ensuring consistent read operation characteristics across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory cell array increases, then memory capacity increases, but RC loading of column selection line and global input/output line increases causing characteristic differences
Solution Approach 1:
The patent applies local quality by dividing the memory cell array into multiple row blocks and applying different operation intervals to different row blocks based on their distance from the column decoder. Memory cells in row blocks closer to the column decoder use a first operation interval, while memory cells in row blocks farther away use a second operation interval. This localized adjustment compensates for the RC loading effects that vary by position, ensuring consistent read operation characteristics across the entire large-capacity memory array.
2Quantity of substance
If memory cell array size increases, then memory capacity increases, but current consumption increases due to higher RC loading
Solution Approach 1:
The patent changes the operation interval parameter based on the position of row blocks within the memory cell array. By adjusting the operation interval according to distance from the column decoder, the system optimizes current consumption for each region. Row blocks farther from the column decoder, which experience higher RC loading, use a longer operation interval to allow sufficient charging time, while row blocks closer to the decoder use a shorter interval, reducing unnecessary current consumption and overall power usage.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.