DRAM Write Protection via Serial Data Buffer Error Checking

The patent introduces a serial data buffer (SDB) device as an intermediary component between the memory device and the interface. The SDB performs error checking and write protection functions, separating the error detection logic from the core memory device. This mediator approach improves data reliability while containing complexity in a dedicated buffer component rather than throughout the entire system.

The patent extracts the error detection and correction functionality into a separate write protection mechanism and SDB device, rather than embedding it within the core memory device. This extraction allows the memory device to maintain simplicity while the dedicated error-checking components handle reliability functions, thus improving data transfer reliability without significantly increasing overall device complexity.

The patent implements preliminary error checking at the SDB device before data is written to the memory core. The write protection mechanism performs CRC checking and error detection in advance, allowing valid data to be written without delay while blocking only erroneous data. This preliminary action approach ensures reliability without adding latency to the overall write path for correct data.

The patent allows data to proceed through the write path rapidly with concurrent read and write operations, skipping unnecessary turnaround delays. The error checking is performed in parallel where possible, and the write protection mechanism quickly validates or rejects data without holding up the data path. This rushing through approach maintains high speed while still providing error detection and correction where needed.

The patent segments the memory device into distinct unidirectional ports for reading and writing operations. By separating read and write paths into dedicated unidirectional interfaces, the device enables concurrent operations without the complexity of bidirectional arbitration logic. Each port is optimized for its specific function, improving productivity while managing complexity through functional segmentation.

The SDB device acts as an intermediary that manages the complexity of concurrent read and write operations. It handles the coordination and error checking for the unidirectional ports, allowing the memory core to focus on data storage while the SDB manages the interface complexity. This mediator approach enables high-productivity concurrent operations without burdening the core memory device with excessive complexity.