DRAM Shaped Word-Line Waveform for Leakage and Speed Trade-Off
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Solution Overview
Problem
Conventional DRAM access transistors face a trade-off between high reliability and performance due to high threshold voltage and thick gate dielectric required for high VPP, leading to longer WRITE or READ times and increased leakage current.
Innovation Solution
A novel shaped word-line waveform design for DRAM cells, where the gate terminal of the access transistor is applied with multiple voltage levels during different phases of the access cycle, reducing the duty cycle of high voltage stress and allowing for thinner gate dielectric materials, thereby improving performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the access transistor is designed with high threshold voltage and thick gate dielectric to sustain high VPP, then reliability is improved, but WRITE and READ operation times increase and performance deteriorates
Solution Approach 1:
The patent applies dynamic voltage adjustment to the word-line, transitioning from a static high VPP approach to a dynamically shaped waveform. The waveform is divided into multiple phases: an initial high-voltage phase for strong transistor activation, followed by a reduced-voltage phase for sustained operation. This dynamic adjustment allows the transistor to achieve both high-speed switching initially and maintain reliability throughout the operation cycle, resolving the contradiction between speed and reliability.
Solution Approach 2:
The patent changes the voltage parameter over time by applying a shaped waveform instead of a constant high voltage. The waveform includes an initial peak voltage for strong transistor turn-on, followed by a reduced voltage level for the remainder of the access cycle. This parameter change allows the transistor to operate with high performance during critical switching moments while reducing stress during sustained operation, thereby improving both speed and reliability.
2Reliability
If the access transistor uses thick gate dielectric material to withstand high VPP stress, then reliability is improved, but leakage current increases and retention time deteriorates
Solution Approach 1:
The patent uses dynamic voltage shaping to apply high voltage only during the initial phase of the access cycle when strong transistor activation is needed, then reduces the voltage for the remainder of the cycle. This temporal separation allows the use of thinner gate dielectric material that would normally be insufficient for high voltage, but becomes adequate because the high voltage is applied briefly and controllably, minimizing leakage current while maintaining reliability.
Solution Approach 2:
The patent implements a periodic shaped waveform on the word-line with distinct phases: an initial high-voltage pulse for transistor activation, followed by a reduced-voltage phase for data retention. This periodic action with controlled timing ensures that high voltage stress is applied only when necessary for switching, while the reduced voltage phase minimizes leakage current and maintains charge retention in the storage capacitor, resolving the contradiction between reliability and leakage.
Data Source
AI summary
A DRAM chip includes a DRAM cell and a first voltage source. The DRAM cell includes an access transistor, and one terminal of the access transistor is coupled to a word line. The first voltage source is selectively coupled to the access transistor via the word line, and generates a first voltage level higher than a sum of a threshold voltage of the access transistor and a voltage level of a signal ONE utilized in the DRAM chip. A whole access cycle includes an access operation period and a restore phase period. When the whole access cycle begins, the one terminal of the access transistor is initially applied by the first voltage level for a first portion of the access operation period and then applied by a second voltage level for a second portion of the access operation period. The second voltage level is lower than the first voltage level.