DRAM Write Circuit Inversion Control for Power Reduction
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Solution Overview
Problem
Dynamic Random Access Memory (DRAM) faces challenges in achieving power-saving while ensuring signal integrity and reliability of data transfer and storage, as existing solutions do not effectively balance these requirements.
Innovation Solution
A write operation circuit for DRAM that includes a data determination module to invert input data based on the number of high data bits, a serial-to-parallel conversion circuit, a data buffer module, and a precharge module, which reduces the number of global bus inversions and thereby minimizes power consumption by setting the initial state of the global bus to low and using a precharge pull-down structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data inversion is performed frequently to maintain signal integrity, then data transfer reliability is improved, but power consumption increases
Solution Approach 1:
The patent changes the parameter of data inversion frequency by introducing a data inversion counter that tracks the number of inversions. When the counter reaches a predetermined threshold, the inversion operation is suspended temporarily. This dynamic adjustment of inversion frequency maintains signal integrity when necessary while reducing power consumption by avoiding excessive inversions.
Solution Approach 2:
The patent implements periodic suspension of data inversion operations based on the inversion count reaching a threshold. Instead of continuous inversion, the system alternates between inverting and suspending inversion operations, creating a periodic action pattern that balances reliability maintenance with power saving.
2Reliability
If data inversion operation is performed to maintain signal integrity, then data transfer reliability is improved, but write current increases
Solution Approach 1:
The patent dynamically changes the inversion operation parameter by introducing a suspension mechanism. When the data inversion counter reaches a predetermined value, the inversion operation is suspended for a predetermined period. This parameter change reduces write current by limiting the frequency of high-current inversion operations while maintaining signal integrity through selective inversion when necessary.
3Reliability
If data inversion is performed frequently to ensure data quality, then data storage reliability is improved, but power consumption increases
Solution Approach 1:
The patent changes the inversion frequency parameter by implementing a counter-based suspension system. The data inversion counter tracks inversion operations, and when it reaches a threshold, inversion is suspended temporarily. This ensures data storage reliability is maintained through adequate inversion while reducing power consumption by preventing excessive inversion operations.
Data Source
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AI summary
Embodiments of the present application provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit comprises: a data determining module, determining, according to the number of bits of high data in input data of a semiconductor memory, whether to flip the input data, so as to generate flip identification data and first intermediate data; a data buffering module, determining whether to flip a global bus according to second intermediate data, wherein the second intermediate data is inverted data of the first intermediate data; a data receiving module, decoding global bus data according to the flip identification data and writing the decoded data into a storage block of the semiconductor memory, the decoding comprising determining whether to flip the global bus data; and a pre-charge module, setting the initial state of the global bus to be low. The technical solutions of the embodiments of the present application can implement reduction in the number of flips of the internal global bus under a pull-down architecture, thereby greatly compressing current and reducing power consumption.