Dry Etch Process for Semiconductor Hard Mask Removal
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Solution Overview
Problem
The miniaturization of semiconductor devices, such as CMOS, poses fabrication challenges due to the need for precise and uniform removal of hard mask layers and spacers, which affects the morphology and performance of the devices.
Innovation Solution
A method involving a dry etch process using NF3 and H2 as etchants, with adjustable flow ratios and temperature steps, is employed to uniformly remove the first hard mask layer and spacer, ensuring a flat morphology and improved performance by controlling etch rates for different materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to remove hard mask layers and spacers during miniaturization, then fabrication can proceed, but uniform removal rates and morphology quality deteriorate
Solution Approach 1:
The patent applies parameter changes by adjusting the flow ratio of NF3 and H2 gases in the dry etch process, and by implementing a two-step temperature protocol (first step <50°C, second step >100°C). These parameter modifications enable uniform removal rates for different materials (first hard mask layer and spacer) while maintaining fabrication feasibility, directly resolving the contradiction between manufacturing precision and ease of manufacture
Solution Approach 2:
The patent employs periodic action through a two-step etching process with distinct temperature conditions. The first step operates at low temperature (<50°C) and the second step at high temperature (>100°C), creating periodic variations in etching conditions that achieve uniform removal of different materials while managing fabrication complexity
2Length of moving object
If miniaturization is pursued to meet demand for smaller devices, then device size decreases, but fabrication difficulty and morphology issues increase
Solution Approach 1:
By changing the etching parameters (gas flow ratio of NF3:H2 and temperature steps), the patent achieves uniform removal rates that maintain morphology quality even as device dimensions are reduced. This allows continued miniaturization while preventing the degradation of manufacturing precision that would otherwise occur
3Manufacturing precision
If selective removal of hard mask layers is performed, then pattern definition is achieved, but overhang structures and point discharge phenomena occur
Solution Approach 1:
The patent changes the etching parameters (NF3:H2 flow ratio and temperature sequence) to achieve uniform removal rates between the first hard mask layer and spacer. This uniformity prevents the formation of overhang structures and eliminates point discharge phenomena while maintaining accurate pattern definition
Solution Approach 2:
The patent replaces conventional etching methods with a specialized dry etch process using NF3 and H2 gases. This substitution of the etching mechanism enables precise control over material removal, achieving uniform rates that prevent harmful structural formations while defining patterns accurately
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a better morphology and improved performance of semiconductor devices by achieving uniform removal rates for various materials, preventing issues like overhang structures and point discharge phenomena.
Implementation Method 1
A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants
Implementation Method 2
the flow ratio of NF3 and H2 is adjusted in the dry etch process so that a remove rate of the first hard mask and the spacer can be adjusted to be substantially the same
Data Source
AI summary
Provided is a method of fabricating a semiconductor device including the following steps. A dummy gate structure is formed on a substrate, wherein the dummy gate structure includes a dummy gate and a stacked hard mask, and the stacked hard mask includes from bottom to top a first hard mask layer and a second hard mask layer. A spacer is formed on a sidewall of the dummy gate structure. A mask layer is formed on the substrate. An opening corresponding to the second hard mask layer is formed in the mask layer. The second hard mask layer is removed. The mask layer is removed. A dry etch process is performed to remove the first hard mask layer, wherein the dry etch process uses NF3 and H2 as etchants.