Directed Self-Assembly Etch Mask for Vertical Nanowire Patterning
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Solution Overview
Problem
The formation of high aspect ratio vertical devices in semiconductor fabrication is limited by lithographic constraints, leading to challenges in improving the performance and scalability of field effect transistors due to the short channel effect and limitations in channel length and contact lengths.
Innovation Solution
The method involves forming vertical nanowires using a directed self-assembly material etch mask, where a hard mask layer is patterned using a directed self-assembly material to expose and etch nanowire material, defining a substantially vertical nanowire with dimensions determined by the intrinsic pitch of the self-assembly material, allowing for decoupling of channel length and contact lengths from lateral device pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and patterning processes are used to form vertical devices, then device fabrication can be performed, but the achievable dimensions are limited by lithographic constraints
Solution Approach 1:
The patent segments the patterning process into multiple steps: first forming mandrels using conventional lithography, then using directed self-assembly to form additional patterns around the mandrels. This segmentation allows the final vertical device dimensions to be defined by the self-assembly material pitch rather than being limited by single-step lithographic resolution, thereby improving manufacturing precision while maintaining ease of manufacture.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structure formation. By forming vertical nanowires and high aspect ratio structures that extend perpendicular to the substrate surface, the invention decouples the lateral pitch from the vertical dimensions, allowing independent optimization of channel length and contact lengths without being constrained by lithographic resolution in the lateral direction.
2Speed
If channel length is decreased to improve switching speed, then FET operating speed improves, but the separation between source and drain regions decreases causing short channel effects
Solution Approach 1:
The patent employs vertical device topology where the channel extends vertically rather than laterally. This dimensional change allows the channel length to be extended in the vertical direction while maintaining short lateral dimensions, thereby achieving fast switching speed without suffering from short channel effects that occur when source and drain are too close together in planar devices.
Solution Approach 2:
The patent segments the channel into multiple vertical sections with different materials or doping profiles along the vertical axis. This allows independent optimization of different channel regions - the upper portion can be optimized for high mobility to enable fast switching, while the lower portion can be optimized for effective source/drain separation to prevent short channel effects.
3Adaptability or versatility
If vertical device topology is used to decouple channel length and contact lengths from lateral device pitch, then scaling and cost reduction benefits are achieved, but the formation of high aspect ratio vertical devices is difficult
Solution Approach 1:
The patent performs preliminary actions by first forming mandrels and then using directed self-assembly to create patterned layers around them before etching the vertical structures. This preliminary patterning provides a template that guides the formation of high aspect ratio vertical devices, making the difficult etching process more controllable and achievable by establishing precise lateral boundaries before vertical material removal.
Solution Approach 2:
The patent uses directed self-assembly materials as an intermediary between the lithographically formed mandrels and the final vertical device structure. This intermediary material with its intrinsic pitch provides a bridging mechanism that translates lateral lithographic patterns into precisely defined vertical dimensions, enabling the formation of high aspect ratio structures with controlled geometry that would otherwise be difficult to achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of vertical nanowires with controlled dimensions, addressing the short channel effect and improving the scalability and performance of semiconductor devices by overcoming lithographic limitations.
Implementation Method 1
a first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
Data Source
AI summary
A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.