DSA Metal Layer Bridging Dots for Transistor Logic
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Solution Overview
Problem
Current lithography techniques are limited in patterning features below 60 nm, with EUV lithography facing challenges in stable light source requirements and high costs, and other methods like spacer or double patterning increasing complexity and cost, while directed self-assembly (DSA) lacks standard cell design methodologies for CMOS transistor cells.
Innovation Solution
The method involves forming a standard transistor layout using DSA pre-patterns and a standard metal layer, with horizontal and vertical metal lines, bridging dots, and specific metal layer structures to determine logic functions, utilizing DSA chemical epitaxy and graphoepitaxy with block copolymers to achieve smaller feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EUV lithography is used to pattern features below 60 nm, then manufacturing precision is improved, but device complexity and cost increase due to stable light source requirements, reflective lenses, high vacuum environment, and ultra-clean manufacturing
Solution Approach 1:
The patent segments the patterning process into two distinct stages: first using conventional lithography to create mandrels at a relaxed pitch, then using spacer deposition and etching to generate the final fine-pitch features. This segmentation allows each stage to operate within its optimal parameter range, avoiding the need for complex EUV systems while achieving sub-60 nm pitch.
Solution Approach 2:
The patent performs preliminary patterning using conventional lithography to create mandrel structures before applying the spacer layer. This preliminary action establishes a template that guides the subsequent spacer formation, enabling the final fine-pitch features to be generated with simpler equipment while maintaining manufacturing precision.
2Manufacturing precision
If spacer or sidewall technology is used to double density and split pitch, then manufacturing precision is improved, but device complexity increases due to extra deposition and etching processes
Solution Approach 1:
The spacer layer serves multiple functions simultaneously: it acts as a pattern transfer template, defines the final feature pitch, and serves as an etch mask for creating the fine-pitch structures. This multi-functionality reduces the need for additional specialized process steps while achieving the desired pitch reduction.
3Manufacturing precision
If double patterning technology is used to double density, then manufacturing precision is improved, but device complexity and cost increase due to multiple optical lithography processes and mask overlay issues
Solution Approach 1:
The patent introduces a spacer layer as an intermediary element between the mandrel structure and the final fine-pitch features. This intermediary spacer serves as a self-aligned template that eliminates mask overlay issues by providing automatic registration through conformal deposition, simplifying the overall patterning process while achieving double pitch reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of transistor cells with half-pitch as small as 10 nm, maintaining critical dimension uniformity and line-edge roughness, reducing layout complexity and costs, and overcoming limitations of current lithography techniques.
Implementation Method 1
DSA uses the self-assembling capability of block copolymers (BCPs) to obtain periodic nano-features on a surface patterned with chemical functionalities or topographies
Implementation Method 2
The BCP self-assembles to form micro-phase separated structures, where the relative length of the polymer chain for either block determines the morphology the material will adopt
Implementation Method 3
After application of the BCPs to the topographically or chemically patterned surfaces, thermal or solvent annealing methods separate the BCPs into the microdomains
Implementation Method 4
For chemical epitaxy, a neutral surface in combination with chemical pinning regions controls the location and orientation of the BCP microdomains
Implementation Method 5
For graphoepitaxy, a neutral surface in combination with topographical features controls the location and orientation of the BCP microdomains
Implementation Method 6
Structures can be formed using the BCP, such as cylinders or lamellae, which can then be transferred through reactive ion etching to a substrate
Data Source
AI summary
Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.