DSA and Sidewall Image Transfer Patterning for Fin Pitch Control
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Solution Overview
Problem
Current directed self-assembly (DSA) processes are limited in forming patterned lines with pitches greater than 1.5 times the natural pitch of the block copolymer, leading to defects and inadequate nanoscale feature formation for both logic and SRAM devices in integrated circuits, which restricts achieving high SRAM cell density.
Innovation Solution
Integration of densely packed semiconductor fins using a DSA process and semi-isolated semiconductor fins using a sidewall image transfer (SIT) process on a single substrate, where a hard mask layer is formed over the dielectric cap layer to fill spaces between transfer layer portions, and spacers are formed on mandrels to create semiconductor fins with varying pitches, enabling both dense and isolated fin formations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DSA process is used to form patterned lines, then densely packed fins with minimum pitch equal to natural pitch can be created, but fins with minimum pitch of 1.5× natural pitch cannot be formed due to defects
Solution Approach 1:
The substrate is divided into two distinct regions: a first region processed by DSA for densely packed fins with pitch equal to the natural pitch of the block copolymer, and a second region processed by SIT for semi-isolated fins with pitch of 1.5× natural pitch. This segmentation allows each region to be optimized for its specific pitch requirement without compromising the other.
Solution Approach 2:
Different patterning processes (DSA and SIT) are applied to different regions of the substrate based on local pitch requirements. The first region uses DSA for maximum density while the second region uses SIT for relaxed pitch requirements, enabling each area to have the quality needed for its specific function.
2Productivity
If DSA process is used for high density patterning, then sub-lithographic line/space patterns can be generated, but design flexibility for varying pitch requirements is restricted
Solution Approach 1:
The integrated circuit substrate is segmented into logic region and SRAM region, with each region receiving appropriate patterning treatment. The DSA process provides high productivity for the logic region while the SIT process provides design flexibility for the SRAM region.
Solution Approach 2:
The patent creates a universal patterning platform that can handle both high-density requirements (DSA) and flexible pitch requirements (SIT) within the same fabrication process flow, making the system adaptable to different device types and pitch requirements.
3Ease of manufacture
If single patterning process is used, then process simplicity is maintained, but inability to satisfy both logic and SRAM pitch requirements occurs
Solution Approach 1:
The DSA and SIT processes are merged into a single integrated fabrication sequence where both patterning methods are applied to the same substrate in succession. The process combines the advantages of both techniques to simultaneously satisfy the pitch requirements of logic and SRAM regions.
Solution Approach 2:
A dielectric cap layer serves as an intermediary structure that enables both DSA and SIT processes to be applied to the same substrate. This intermediate layer facilitates the formation of different fin structures in different regions without interfering with each other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of semiconductor fins with desired pitches in both logic and SRAM regions, enhancing SRAM cell density and processing flexibility by combining DSA and SIT processes on a single substrate.
Implementation Method 1
Directed self-assembly (DSA) is a patterning technique that generates sub-lithographic line/space patterns through microphase separation of a block copolymer
Implementation Method 2
The top semiconductor layer is subsequently patterned using the transfer layer portions and the spacers as an etch mask
Data Source
AI summary
After forming transfer layer portions over a portion of a dielectric cap layer overlying a first portion of a substrate by a directed self-assembly process, a hard mask layer is formed over the dielectric cap layer to fill spaces between the transfer layer portions. Spacers are then formed over a portion of the hard mask layer overlying a second portion of the substrate by a sidewall image transfer process. A top semiconductor layer of the substrate is subsequently patterned using the transfer layer portions and the spacers as an etch mask to provide densely packed semiconductor fins in the first region and semi-isolated semiconductor fins in the second region of the substrate.