Configurable Domain Specific Abstract Core for Embedded Power Efficiency
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Solution Overview
Problem
Current embedded application designs face limitations in achieving flexibility similar to software implementations while maintaining the speed of hardware implementations, particularly in power-constrained environments, due to the trade-off between generality and power efficiency.
Innovation Solution
A configurable domain-specific abstract core (DSAC) is introduced, comprising function-specific abstract modules, micro state engines, buffer modules, and programmable data path connections, allowing for dynamic configuration at various stages to optimize data flow and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a microprocessor based design is used to achieve flexibility, then adaptability is improved, but speed deteriorates
Solution Approach 1:
The system segments processing instructions into two categories: those implemented in hardware (FPGA/ASIC) for speed-critical tasks and those implemented in software on a microprocessor for flexibility. This segmentation allows each component to operate at its optimal speed while maintaining overall system flexibility through the software portion.
Solution Approach 2:
The system employs dynamic configuration capabilities where the microprocessor can reconfigure hardware resources at runtime based on application requirements. This dynamic approach allows the system to adapt its architecture flexibly while maintaining high-speed processing through hardware acceleration when needed.
2Speed
If clock speed of microprocessor is raised to increase computation speed, then speed is improved, but power consumption increases
Solution Approach 1:
The system segments computational tasks between hardware and software, allowing speed-critical operations to run in hardware at lower clock speeds while less time-sensitive operations run in software. This segmentation reduces the overall power consumption compared to running all tasks at high speed on a microprocessor.
Solution Approach 2:
The system changes the operational parameters by implementing a hybrid architecture where different types of processing instructions are executed at different speeds and in different locations (hardware vs. software). This parameter change allows the system to achieve required performance levels without uniformly high clock speeds, thereby reducing power consumption.
3Speed
If hardware implementation is used to achieve high speed computation, then speed is improved, but adaptability deteriorates
Solution Approach 1:
The system implements a universal hybrid architecture that can handle both hardware-accelerated and software-based processing instructions. The microprocessor component provides universal adaptability to execute various algorithms, while the hardware component provides universal high-speed processing for computational tasks, making the system versatile across different application domains.
Solution Approach 2:
The system employs dynamic configuration capabilities where the microprocessor can reconfigure hardware resources at runtime based on application requirements. This dynamic approach allows the system to adapt its architecture flexibly while maintaining high-speed processing through hardware acceleration when needed.
4Productivity
If multi-core SoC is used to achieve high performance at lower clock speeds, then productivity is improved, but power consumption increases
Solution Approach 1:
The system segments processing instructions into hardware and software components, allowing critical path operations to be accelerated in hardware while other operations run in software. This segmentation achieves high productivity without requiring multiple full-featured CPU cores, thereby reducing overall power dissipation compared to multi-core SoC approaches.
Solution Approach 2:
The system changes the operational parameters by implementing a hybrid architecture where different types of processing instructions are executed at different speeds and in different locations (hardware vs. software). This parameter change allows the system to achieve required performance levels without uniformly high clock speeds, thereby reducing power consumption.
Data Source
AI summary
The present invention provides a configurable domain specific abstract core (DSAC) for implementing applications within any domain. The DSAC comprises at least one function specific abstract module (FSAM) configurable at a plurality of stages for implementing a predetermined function belonging to one or more applications in the domain. The FSAM comprises a function specific abstract logic (FSAL) for implementing functional logic and a micro state engine (MSE) for generating and monitoring one or more control signals, at least one of the control signals being generated by execution of a dynamic script for controlling the FSAL. The DSAC further comprises one or more buffer modules for data exchange among one or more FSAMs, and for temporary storage of data, one or more programmable data path connection maps comprising a set of interconnections, for configuring data paths among the one or more FSAMs and the one or more buffers, and a programmable hardware software interface module for coupling with one or more external computing devices. The DSAC may be configured at a design configuration stage, an application initialization configuration stage and a run time configuration stage. The DSAC implements a data driven control flow architecture.