DSAC Latch Comparison Circuitry for Faster Scan Chain Fault Detection
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Solution Overview
Problem
Highly integrated electronic systems, such as SoCs, face challenges in testing and validation due to complex scan chains that can increase the likelihood of failures and require extensive time to detect improper operations, especially under power fluctuations and signal propagation variations.
Innovation Solution
The introduction of Data Scan and Compare (DSAC) latches with active feedback circuitry that compares input and output states asynchronously, allowing for quick error detection and notification, thereby reducing the complexity of fault detection and enabling faster remedial actions without relying on system clock delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If scan chains are used to test latched data in highly integrated systems, then the ability to access and test internal nodes is improved, but the complexity of testing increases and the time required to detect failures increases
Solution Approach 1:
The patent divides the scan chain into segments with intermediate comparison points. Instead of testing all latches sequentially from one end, the scan chain is divided into multiple segments with comparison latches positioned at intermediate points, allowing parallel comparison operations and reducing the time to detect faults in specific segments.
Solution Approach 2:
The patent implements preliminary comparison operations by introducing comparison latches that continuously compare input data with latched data as the scan chain operates. This allows fault detection to occur during normal scan operations rather than requiring a separate complete test cycle, reducing overall testing time.
2Reliability
If scan chains with many serially scanned devices are used to increase functionality, then the coverage of testing is improved, but the likelihood of failures increases and the time to determine improper operation increases
Solution Approach 1:
The patent segments the long scan chain into smaller functional units with comparison latches at strategic points. This segmentation reduces the effective complexity of any single test operation by limiting the number of latches that need to be sequentially examined when a fault is detected, while maintaining comprehensive coverage of all devices.
Solution Approach 2:
The patent introduces comparison latches as intermediary elements between the main scan chain latches and the test equipment. These comparison latches act as mediators that perform local comparisons and generate fault indicators, simplifying the overall test architecture by distributing the comparison function across multiple intermediate points rather than requiring centralized analysis of all latches.
3Ease of manufacture
If traditional scan chain methods are used to read latched data, then the simplicity of implementation is maintained, but the speed of error detection is reduced due to sequential clocking requirements
Solution Approach 1:
The patent performs preliminary comparison operations within the scan chain structure itself using comparison latches that operate in parallel with the main data latches. This allows fault detection to occur during the normal data capture phase rather than requiring a separate sequential read phase, significantly improving error detection speed while maintaining the basic scan chain implementation.
Solution Approach 2:
The patent maintains continuous comparison operations throughout the scan chain operation. The comparison latches continuously compare input data with latched data as data flows through the chain, eliminating idle periods where no detection is occurring. This continuous operation improves detection speed without adding complex interrupt or polling mechanisms.
Data Source
AI summary
In described examples, a latch includes active feedback circuitry for latching input information. A comparison of logic states between input and output states at selected times can determine whether, for example, the latch has correctly retained latch data. The latch can optionally be included within a scan chain, provide asynchronous latch error notifications, and/or synchronous notifications indicating where in the scan chain a latch error occurred.