DSB Operation Segmentation for Long-Latency PCIe Accesses
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Solution Overview
Problem
Existing DSB operations are negatively impacted by long latency load/store operations, particularly those targeting PCIe addresses, causing delays in processor execution due to the requirement of completing all outstanding operations before proceeding.
Innovation Solution
Implementing a mild DSB operation that excludes the completion of load/store operations targeting specific memory regions, such as PCIe addresses, allowing processors to acknowledge completion without waiting for these operations, and enabling parallel processing of different types of DSB operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a processor waits for all outstanding load/store operations to complete before acknowledging DSB completion, then data consistency is ensured, but processor execution speed deteriorates due to long latency operations
Solution Approach 1:
The patent segments the memory address space into excluded regions (e.g., PCIe address space) and non-excluded regions. The DSB operation is then segmented into two independent tracking mechanisms: one for excluded region operations (which do not block) and another for non-excluded region operations (which must complete). This segmentation allows the processor to acknowledge DSB completion for non-excluded regions without waiting for long-latency excluded region operations, thus resolving the contradiction between data consistency and execution speed.
Solution Approach 2:
The patent extracts long-latency load/store operations targeting excluded regions from the DSB completion condition. By removing these operations from the completion criteria, the processor can acknowledge DSB completion much faster, improving execution speed while maintaining data consistency for the critical non-excluded regions. The excluded region operations are still tracked separately to ensure they eventually complete without blocking the main execution flow.
2Reliability
If a processor completes all outstanding load/store operations before responding to DSB, then correctness is maintained, but system productivity deteriorates due to waiting delays
Solution Approach 1:
The patent segments the completion tracking into two independent counters: an excluded region operation counter and a non-excluded region operation counter. The DSB completion response is triggered when the non-excluded counter reaches zero, allowing the system to maintain correctness for critical operations while improving productivity by not waiting for excluded region operations. This segmentation enables parallel progression of excluded region operations without blocking overall system productivity.
Solution Approach 2:
The patent implements partial completion action by allowing DSB completion to be acknowledged once critical non-excluded region operations are complete, even if excluded region operations are still outstanding. This partial completion approach maintains sufficient correctness for system operation while significantly improving productivity by eliminating unnecessary waiting delays for low-priority excluded region operations.
3Device complexity
If sequential processing of DSB operations is used, then simplicity is maintained, but execution time increases due to lack of parallelism
Solution Approach 1:
The patent segments DSB operation processing into separate handling paths for excluded region operations and non-excluded region operations. Each path has its own completion counter and tracking mechanism, allowing them to be processed independently and in parallel. This segmentation maintains sufficient simplicity by using familiar counter-based completion tracking while dramatically reducing completion time through parallel execution of different DSB operation types.
Solution Approach 2:
The patent adds a new dimension to DSB processing by introducing the exclusion region concept, which creates independent completion tracking in a separate operational dimension. Excluded region operations and non-excluded region operations execute in parallel dimensions rather than sequentially, reducing overall completion time while maintaining processing simplicity through independent counter management.
Data Source
AI summary
Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.