DSD Decoder Silent Pattern Generator for Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DSD decoders face challenges in reducing radiation noise during mute states, particularly when using repeated silent patterns, and compatibility issues arise when different vendors' D/A converters mismatch silent patterns.
Innovation Solution
A DSD decoder with a silent pattern generator that outputs different silent patterns in a time division manner, each with a 50% mark rate, and a DMA controller that switches bit arrangement modes based on flags in the file header to reduce processor load and power consumption, while ensuring compatibility with various D/A converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same silent pattern is repeated during mute state, then the mute function is achieved, but radiation noise increases
Solution Approach 1:
The patent applies periodic action by generating different silent patterns at regular intervals during the mute state instead of repeating the same pattern. The silent pattern generator switches between multiple patterns (e.g., Pattern 1, Pattern 2, Pattern 3) in a periodic manner, which spreads the spectral energy and reduces radiation noise while maintaining the mute function.
Solution Approach 2:
The patent implements dynamics by making the silent pattern variable rather than static. The system dynamically switches between different silent patterns based on a counter or timing mechanism, transforming the static repeated pattern into a dynamic changing pattern sequence, thereby reducing noise radiation.
2Reliability
If a control signal line is added for mute control, then the mute function is achieved, but device complexity increases
Solution Approach 1:
The patent merges the mute control function with the existing bit stream data transmission path. Instead of adding a separate control signal line, the system conveys mute state information through the data lines already present in the audio system, using the same physical medium for both data and control information.
Solution Approach 2:
The patent makes the existing data transmission lines multi-functional by using them to carry both audio data and mute control information. The bit stream data lines serve dual purposes: transmitting audio signals during playback and conveying mute state during silence periods, eliminating the need for dedicated control lines.
3Adaptability or versatility
If processor frequency is increased to handle bit arrangement switching, then compatibility is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-arranging the bit order according to the file header specification before processing. The system reads the bit arrangement flag in advance and configures the silent pattern generator accordingly, so that no real-time processing or frequency adjustment is needed during operation, thereby reducing power consumption.
Solution Approach 2:
The system uses the file header information to automatically configure its own operation mode. The bit arrangement flag in the file header self-describes the required processing mode, and the system automatically adapts without external intervention or complex control logic, reducing the processing burden and power consumption.
Data Source
AI summary
A decoder that decodes DSD (Direct Stream Digital) data including: a memory storing the DSD data; a processor; a DMA (Direct Memory Access) controller configured to read the DSD data from the memory one word at a time according to a command from the processor; a parallel/serial converter configured to output a plurality of bits contained in a word read by the DMA controller in a bit stream format; and a silent pattern generator configured to selectively output a plurality of silent patterns in a time division manner during a silence period, wherein each of the plurality of silent patterns has a mark rate of 50% and is a string of bits having different values.