DSD Audio Volume Circuit Without PCM Conversion Delay

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Solution Overview

Problem

Native playback of DSD signals lacks volume control capabilities, which limits sound quality and introduces delays due to the need for PCM conversion.

Innovation Solution

An audio circuit with an N-bit shift register and a replacement circuit that substitutes (N-M) bits with a mute bit string having a 50% mark rate, allowing for volume control in the DSD native format without PCM conversion, using a pseudo-random bit sequence or inverted mute bit string to maintain sound quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If native playback is used to maintain high sound quality, then sound quality is improved, but volume control capability deteriorates

Engineering Contradiction:
Improvesound qualityVSAvoidvolume control capability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent segments the DSD signal processing into two independent parts: the high-quality native DSD playback path and the volume control path. The volume control is implemented by selectively muting specific bit positions in the DSD data stream using a gain control circuit, rather than converting the entire signal to PCM. This segmentation allows volume control to be applied to the DSD signal without compromising the overall sound quality of native playback.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a gain control circuit as an intermediary component between the DSD data input and the output. This intermediary processes the DSD data by selectively replacing bits with mute bits based on the desired volume level, enabling volume control without direct PCM conversion. The gain control circuit acts as a mediator that preserves the DSD format while implementing volume adjustment.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If PCM conversion is performed to enable volume control, then volume control capability is improved, but processing delay and jitter susceptibility worsen

Engineering Contradiction:
Improvevolume control capabilityVSAvoidprocessing delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent extracts the volume control function from the PCM conversion process. Instead of converting DSD to PCM and then applying volume control, the invention extracts and implements volume control directly on the DSD signal using a gain control circuit that selectively mutes bits in the DSD data stream. This eliminates the time-consuming PCM conversion step while preserving volume control capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If PCM conversion is performed to enable volume control, then volume control capability is improved, but power consumption and circuit complexity worsen

Engineering Contradiction:
Improvevolume control capabilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional approach by not converting DSD to PCM, but instead applying volume control directly to the DSD signal. The gain control circuit inverts the traditional signal processing chain by operating on the DSD bits directly, replacing specific bits with mute bits based on the desired volume level. This inversion simplifies the circuit by eliminating the PCM conversion infrastructure while achieving the same volume control function.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS12167213B2Audio circuit, and reproduction method of DSD signal
Publication Date: 2024.12.10 ROHM CO LTD
  • US12167213B2 patent drawing
  • US12167213B2 patent drawing
  • US12167213B2 patent drawing

AI summary

The audio circuit has a volume circuit structured to process a DSD signal that contains DSD data and a DSD clock. The volume circuit has a first shift register and a replacement circuit. The first shift register holds N bits of the DSD data. The replacement circuit replaces (N−M) bits (0≤M≤N) corresponding to a gain set value, out of N bits stored in the first shift register, with a mute bit string having a mark rate of substantially 50%.