Die-Stacked DRAM Memory Subsystem with Software Page Allocation
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Solution Overview
Problem
Conventional memory subsystems face inefficiencies in reducing memory access latency and cache misses due to hardware-based cache management, which limits performance improvements.
Innovation Solution
A die-stacked DRAM (DSDRAM) system is implemented, where frequently accessed memory pages are stored in both DRAM chips separate from the processor and DSDRAM on a silicon interposer, with a dedicated interface and software-controlled page allocation, eliminating the need for cache tags and allowing for full associativity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware-based cache management is used, then memory access speed is improved, but system complexity and overhead increase
Solution Approach 1:
The patent replaces the hardware-based cache management system with a software-based memory management approach. Instead of using complex hardware cache controllers, tag management, and hardware monitoring logic, the invention uses the operating system's page table mechanisms and software page fault handlers to achieve cache-like functionality. This substitution eliminates hardware complexity while maintaining memory access performance through software-controlled page allocation and duplication strategies.
2Loss of information
If cache tags are implemented, then cache line identification is improved, but memory overhead and access latency increase
Solution Approach 1:
The patent extracts the tag management functionality from the hardware cache system and relocates it to the software memory management layer. Instead of storing tags in hardware cache structures alongside data, the invention uses the operating system's page table entries and virtual memory mechanisms to track and identify memory pages. This extraction eliminates the overhead of hardware tag storage and access, reducing memory access latency while maintaining accurate page identification through software data structures.
3Adaptability or versatility
If fully associative memory structure is used, then memory access flexibility is improved, but hardware complexity increases
Solution Approach 1:
The patent replaces the hardware fully associative memory structure with a software-based virtual memory system. Instead of implementing complex hardware comparison logic that checks all cache lines simultaneously, the invention uses the operating system's page table and virtual address translation mechanisms to provide flexible memory access. The software can dynamically allocate and manage memory pages with full associativity, eliminating the need for complex hardware comparison circuits while maintaining the flexibility to access any memory location.
4Productivity
If die-stacked DRAM is implemented, then memory bandwidth is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory system into two distinct physical components: die-stacked DRAM for high-bandwidth memory operations and separate DRAM chips for additional capacity. This segmentation allows each memory component to be manufactured and optimized independently using established manufacturing processes, reducing the overall manufacturing complexity compared to a fully integrated solution. The segmented architecture enables the system to achieve high bandwidth through the die-stacked portion while maintaining ease of manufacture by using standard DRAM chips for the remainder of the memory system.
Data Source
AI summary
A memory subsystem incorporating a die-stacked DRAM (DSDRAM) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (IC) package, a DSDRAM coupled to the processor, the DSDRAM implemented on the silicon interposer of the IC package, and a DRAM implemented separately from the IC package. The DSDRAM and the DRAM form a main memory having a contiguous address space comprising a range of physical addresses. The physical addresses of the DSDRAM occupy a first contiguous portion of the address space, while the DRAM occupies a second contiguous portion of the address space. Each physical address of the contiguous address space is augmented with a first bit that, when set, indicates that a page is stored in the DRAM and the DSDRAM.