Dual Stress Liner Border Orientation for Transistor Drive Current

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Transistor performance in integrated circuits does not scale with technology advancements, and existing dual stress liner (DSL) technology requires optimization to enhance both PMOS and NMOS transistor performance effectively.

Innovation Solution

The placement of dual stress liner borders is optimized by positioning them perpendicular to the transistor gates primarily inside the nwell and parallel to the transistor gates primarily outside the nwell, with specific spacing rules to maximize PMOS and NMOS drive current gains, using PECVD silicon nitride films to apply compressive and tensile stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If DSL border is positioned inside the nwell perpendicular to gates, then PMOS performance is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvetransistor drive currentVSAvoidDSL border placement complexity

Core Design Contradiction:

PowerVSDevice complexity

Solution Approach 1:

The DSL border positioning is predetermined and integrated into the standard CMOS fabrication process flow. The compressive and tensile stress liner regions are formed during normal manufacturing steps with pre-planned patterning and deposition sequences, avoiding the need for additional complex alignment or positioning steps that would increase manufacturing complexity

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances PMOS drive current by moving the DSL border closer to the p-active region and improves NMOS drive current by adjusting its distance from the n-active region, resulting in significant gains in transistor performance as demonstrated by experimental data.

Implementation Method 1

Compressive stress enhances hole mobility when applied parallel to the current flow in a PMOS transistor. One method to apply compressive stress in PMOS transistors is to remove silicon from the source and drain regions and replace it with epitaxially grown silicon germanium (SiGe).

Methodology Applied

Scientific EffectCompressive stress: Compression

Implementation Method 2

For NMOS transistors, applying tensile stress either perpendicular or parallel to the current flow enhances electron mobility. One method of applying tensile stress to the channel region in an NMOS transistor is to deposit a tensile contact etch stop layer over the NMOS transistor.

Methodology Applied

Scientific EffectTensile stress: Tension

Implementation Method 3

Germanium is a larger atom than silicon so the lattice constant of crystalline SiGe is greater than crystalline Si applying compressive stress to the PMOS channel region.

Methodology Applied

Scientific EffectLattice mismatch stress: Epitaxy

Data Source

PatentUS9953967B2Integrated circuit with dual stress liner boundary

Publication Date: 2018.04.24 TEXAS INSTRUMENTS INC

AI summary

An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.