Dual Stress Liner Void Prevention in MOSFET Fabrication
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Solution Overview
Problem
As semiconductor devices shrink, voids or gaps can occur in stress-inducing dielectric layers during the UV curing process, leading to undesired metal leads and potential device shortening due to differences in material expansion rates, which affects the yield and performance of MOSFETs.
Innovation Solution
A method is developed to fabricate semiconductor devices with a dual stress liner (DSL) by forming a tensile stress-inducing dielectric layer and a compressive stress-inducing dielectric layer on complementary MOS transistors, followed by removing the capping layers before subsequent processes to prevent voids and gaps, thereby enhancing the yield and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a UV curing step is performed to make the SiN dielectric layer gain stress to improve carrier mobility, then the carrier mobility of the transistor is improved, but voids or gaps occur in the material layers due to stress gain and difference of expansion rate between different material layers
Solution Approach 1:
The patent changes the stress parameter of the dielectric layer by performing a UV curing step on the SiN layer, transforming it from an unstressed state to a stressed state. This parameter change improves carrier mobility while the patent manages the associated void formation through process control
Solution Approach 2:
The patent converts the harmful effect of void formation into a beneficial process by designing the voids to occur in controlled locations and using them as part of the stress-inducing mechanism. The voids formed during UV curing are utilized to enhance the stress effect on the channel while maintaining device functionality
2Reliability
If stress-inducing dielectric layers are formed to improve transistor performance, then carrier mobility is enhanced, but undesired metal leads occur on metal lines or plugs generated by subsequent interconnection process and extend along voids
Solution Approach 1:
The patent performs preliminary actions by forming the stress-inducing dielectric layer with controlled voids before the interconnection process. This preliminary structuring allows subsequent metal deposition to occur in a controlled manner, preventing undesired metal lead formation while maintaining the stress effect
Solution Approach 2:
The patent uses the void structure as an intermediary element that mediates between the stress-inducing dielectric layer and the subsequent interconnection process. The voids serve as a buffer that prevents direct contact and potential shorting between metal leads while allowing the stress effect to propagate to the channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively prevents metal leads from extending into voids and gaps, increasing the yield and performance of semiconductor devices by ensuring a stable interconnection process and improving carrier mobility.
Implementation Method 1
an ultra-violate (UV) curing step is then performed to make the SiN dielectric layer gradually gaining a stress
Implementation Method 2
a first stress-inducing dielectric layer and a first capping layer are formed on the first conductive-type MOS transistor in sequence... the first stress-inducing dielectric layer is a tensile stress-inducing dielectric layer... the second stress-inducing dielectric layer is a compressive stress-inducing dielectric layer
Data Source
AI summary
A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.