Dual Stress Liner Via Etching Process
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Solution Overview
Problem
Conventional CMOS fabrication techniques face challenges in etching via contact openings through dual stress liner (DSL) structures, leading to over-etching and defects in non-overlapped regions, which damages underlying metal silicide contacts and affects device performance.
Innovation Solution
An improved etching process flow is introduced, involving the formation of partial via holes and the use of sacrificial materials to selectively etch stress liner layers, allowing for concurrent etching in both overlapped and non-overlapped regions without over-etching, thereby protecting the underlying contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form via contact openings through the DSL structure, then the via contacts can be formed to the underlying contacts, but over-etching occurs in non-overlapped regions causing damage to the metal silicide contacts
Solution Approach 1:
The etching process is divided into multiple selective etching steps, each targeting specific stress liner layers in different regions (overlapped vs. non-overlapped). The first etching step removes the second stress liner layer in overlapped regions, while the second etching step removes the first stress liner layer in non-overlapped regions. This segmentation allows precise depth control for via contacts in different regions, preventing over-etching damage to underlying silicide contacts.
2Reliability
If the etching process is extended to ensure via contacts reach the underlying contacts in overlapped regions, then complete contact formation is achieved, but the underlying contacts in non-overlapped regions are over-etched and damaged
Solution Approach 1:
Different etching conditions and selectivities are applied to different regions of the DSL structure. The first etching step uses selectivity to etch the second stress liner layer faster than the first stress liner layer, ensuring via contacts in overlapped regions reach the underlying contacts. The second etching step uses different selectivity to remove the first stress liner layer in non-overlapped regions without damaging the underlying contacts. This local quality approach ensures complete and precise contact formation in both regions.
3Ease of manufacture
If a single etching step is used for both overlapped and non-overlapped regions, then the process is simpler, but the different thicknesses of DSL structures cause over-etching in non-overlapped regions
Solution Approach 1:
The first etching step is performed as a preliminary action to remove the second stress liner layer in overlapped regions before the second etching step removes the first stress liner layer in non-overlapped regions. This preliminary action prepares the structure for the subsequent etching step, ensuring that via contacts in overlapped regions are already formed to the correct depth before the second etching step begins, preventing over-etching in non-overlapped regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms via contact openings to underlying salicided contacts in both overlapped and non-overlapped regions of the DSL structure, mitigating defects and ensuring reliable contact formation without damaging the silicide layers.
Implementation Method 1
an etching process is performed to selectively etch portions of the second stress liner layer exposed through the partial via holes in the overlapped region of the DSL structure to extend the partial via holes in the overlapped region down to the underlying first stress liner, and concurrently etch portions of the first and second stress liner layers exposed through the partial via holes in the overlapped and non-overlapped regions of the DSL structure to form via contact holes that extend to underlying via contact regions
Data Source
AI summary
Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.