Cache Coherence Flush for Distributed Shared Memory
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Solution Overview
Problem
In distributed shared memory (DSM) systems, maintaining cache coherence across nodes is challenging due to the burden being left to application software, leading to stale data issues when multiple nodes access and modify the same memory region.
Innovation Solution
A mechanism is introduced to flush memory ranges using a single instruction that invalidates all cache lines within a specified address range, ensuring data consistency by copying the range from the processor cache to memory via direct memory access (DMA) and issuing invalidate commands to caching agents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the burden of cache coherence is left to application software in DSM systems, then device complexity is reduced and ease of operation is improved, but data consistency deteriorates due to stale data in caches
Solution Approach 1:
The patent introduces a cache coherence mechanism as an intermediary between the application software and the distributed memory system. This mechanism includes cache invalidation requests and responses that mediate data consistency without requiring application software to manage coherence manually, thus maintaining reliability while keeping the system relatively simple
Solution Approach 2:
The patent implements a feedback mechanism where cache invalidation requests are sent from the home node to remote nodes, and invalidation responses are returned to confirm cache line invalidation. This feedback loop ensures data consistency is maintained automatically without burdening application software
2Productivity
If multiple nodes access and modify the same memory region simultaneously, then productivity is improved through parallel access, but data consistency deteriorates due to stale data remaining in caches
Solution Approach 1:
The patent employs preliminary action by invalidating cache lines in advance before they can cause consistency problems. When a node gains write permission to a memory region, the home node proactively sends invalidation requests to all nodes that may have cached copies, ensuring stale data is cleared before new writes occur
Solution Approach 2:
The cache coherence mechanism acts as an intermediary that coordinates access between multiple nodes. It manages the invalidation process automatically, allowing parallel access while maintaining consistency without requiring application software to implement complex synchronization protocols
3Reliability
If cache lines are invalidated individually, then data consistency is maintained, but processing time increases due to multiple separate operations
Solution Approach 1:
The patent merges multiple individual cache invalidation operations into a single batch operation. The cache invalidation instruction can specify a range of memory addresses, and the system processes all invalidations within that range in one unified operation rather than sending separate invalidation requests for each cache line, significantly reducing processing time
Data Source
AI summary
Embodiments provide for a processor including a cache a caching agent and a processing node to decode an instruction including at least one operand specifying an address range within a distributed shared memory (DSM) and perform a flush to a first of a plurality of memory devices in the DSM at the specified address range.