DSP Block Adder Circuit for Fixed and Floating-Point Operations
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Solution Overview
Problem
Existing programmable logic devices (PLDs) lack direct integration of floating-point operators, particularly due to the resource-intensive nature of carry-propagate adders required for large addition operations in floating-point multiplication, which hinders efficient processing of floating-point operations within specialized processing blocks like DSP blocks.
Innovation Solution
Incorporating an adder circuit capable of both fixed-point and floating-point addition into DSP blocks, allowing simultaneous computation of sum, sum-plus-1, and sum-plus-2 results, which can be selectively used for both fixed-point and floating-point operations, thereby reducing the need for additional carry-propagate adders and maintaining backward compatibility with fixed-point functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If floating-point operators are incorporated into specialized processing blocks, then floating-point operation capability is improved, but area and latency increase due to expensive carry-propagate adders
Solution Approach 1:
The adder circuit is designed to perform multiple functions: it can operate as a carry-propagate adder for floating-point operations when needed, and as a carry-save adder for fixed-point operations. The same circuit hardware is controlled by mode signals to switch between these different operational modes, eliminating the need for separate dedicated adder circuits for each operation type.
Solution Approach 2:
The adder circuit incorporates dynamic control mechanisms through mode selection signals that change the operational behavior of the circuit based on the required operation type. The circuit can dynamically switch between carry-propagate and carry-save modes, allowing flexible adaptation to different computational requirements without physical reconfiguration.
2Adaptability or versatility
If floating-point operators are incorporated into specialized processing blocks, then floating-point operation capability is improved, but operation latency increases due to carry-propagate adder requirements
Solution Approach 1:
The adder circuit incorporates dynamic control mechanisms through mode selection signals that change the operational behavior of the circuit based on the required operation type. The circuit can dynamically switch between carry-propagate and carry-save modes, allowing flexible adaptation to different computational requirements without physical reconfiguration.
Solution Approach 2:
The addition operation is segmented into two stages: the first adder performs carry-save addition to produce partial sums quickly, and the second adder performs the final carry-propagate addition only when needed for floating-point operations. This segmentation allows the system to avoid the full latency of carry-propagate addition for operations that don't require it.
3Adaptability or versatility
If separate floating-point adders are added to DSP blocks, then floating-point addition capability is improved, but device complexity increases
Solution Approach 1:
The adder circuit is designed to perform multiple functions: it can operate as a carry-propagate adder for floating-point operations when needed, and as a carry-save adder for fixed-point operations. The same circuit hardware is controlled by mode signals to switch between these different operational modes, eliminating the need for separate dedicated adder circuits for each operation type.
Data Source
AI summary
Circuitry for performing arithmetic operations on a plurality of inputs efficiently performs both fixed-point operations and floating-point operations. Each of at least first and second respective operator circuits operates on a respective subplurality of the plurality of inputs. Other circuitry selectively interconnects the respective operator circuits so that they can operate together or separately, according to user selection, on selected ones of (a) the full plurality of inputs, (b) individual ones of the respective subpluralities of the plurality of inputs, or (c) combinations of portions of the respective subpluralities of the plurality of inputs. At least one of the respective operator circuits includes circuits for simultaneously computing multiple different results and for selecting among the multiple different results based on an output of another one of the respective operator circuits. One or more of the multiple different results are selectably usable to perform both fixed-point operations and floating-point operations.


