Configurable DSP Block Merging AI Tensor Operations
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Solution Overview
Problem
Existing digital signal processing (DSP) blocks and artificial intelligence (AI) tensor blocks in integrated circuits use incompatible arithmetic architectures, making it difficult to perform both digital signal processing and AI operations on the same device efficiently.
Innovation Solution
A DSP block that combines features of regular DSP blocks and AI tensor blocks, supporting multiple precisions and dataflows, allowing for the creation of larger multipliers from smaller ones, and is backwards compatible with existing FPGA devices, enabling efficient performance of both digital signal processing and AI operations within the same area as previous solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate DSP blocks and AI tensor blocks are used, then each block can be optimized for its specific function, but the device requires more area and has higher complexity
Solution Approach 1:
The patent combines DSP block and AI tensor block functionalities into a single unified arithmetic block. The arithmetic block contains configurable multipliers and adders that can be programmed to perform either DSP operations (such as FIR filtering) or AI tensor operations (such as matrix multiplication), eliminating the need for separate dedicated blocks and reducing overall device complexity while maintaining functional optimization through configurable operation modes
Solution Approach 2:
The arithmetic block is designed with universal functionality to perform multiple types of operations. By configuring the multipliers and adders with programmable parameters, the same hardware resources can execute different algorithms including DSP filters, neural network convolutions, and other mathematical operations, allowing one block to replace multiple specialized blocks
2Adaptability or versatility
If multiple precisions and dataflows are supported, then the DSP block can perform both DSP and AI operations, but the arithmetic architecture becomes more complex
Solution Approach 1:
The arithmetic block employs dynamic configuration capabilities where the multiplier precision, adder configuration, and dataflow patterns can be programmed and changed at runtime. This allows the same hardware structure to adapt between different precision requirements (e.g., INT8 for AI, higher precision for DSP) and different operational modes without requiring multiple fixed-architecture blocks, managing complexity through programmability rather than hardware duplication
Data Source
AI summary
Integrated circuit devices, methods, and circuitry for a digital signal processing (DSP) block that can selectively perform higher-precision DSP multiplication operations or lower-precision AI tensor multiplication operations. Flexible digital signal processing circuitry may include hardened multipliers, hardened summation circuitry, and an intermediate multiplexer network. The intermediate multiplexer network may be configurable to, in a first configuration, route data between the plurality of hardened multipliers and the hardened summation circuitry to perform a plurality of lower-precision multiplication operations. In a second configuration, the intermediate multiplexer network may route the data between the plurality of hardened multipliers and the hardened summation circuitry to perform at least one higher-precision multiplication operation.