DSP Block Enhancement for Standard-Compliant Double Precision Multiplication
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Solution Overview
Problem
Existing digital signal processing (DSP) systems require a high number of processing blocks to perform double precision multiplication, which is resource-intensive and non-compliant with standards like IEEE 754, OpenCL, and ADSPB, especially for calculations involving multiple multiplications.
Innovation Solution
The system employs a scheme using six processing blocks to perform 63×63 multiplication, partitioning numbers into components and computing partial products using a combination of 27×27, 36×36, and 27×9 multiplications, with selection circuitry and modified multipliers to achieve standard-compliant results with reduced resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard double precision multiplication is implemented using conventional DSP blocks, then IEEE 754 and OpenCL compliance is achieved, but the number of processing blocks required increases significantly
Solution Approach 1:
The patent segments the double precision multiplication operation into multiple partial products (P0, P1, P2, P3) that can be computed using smaller multiplier units. Each partial product corresponds to specific bit ranges of the input operands, allowing the overall 64-bit multiplication to be distributed across multiple smaller computational units rather than requiring a single large multiplier block
Solution Approach 2:
The patent implements a hierarchical structure where smaller multiplier units (computing partial products) are nested within a larger multiplication framework. The partial products from smaller units are then combined through addition operations to produce the final double precision result, creating a nested computational structure that reduces the need for large processing blocks
2Reliability
If multiple DSP blocks are used to perform double precision multiplication, then standard compliance is maintained, but resource utilization efficiency decreases
Solution Approach 1:
The patent merges multiple partial product computations into a unified addition structure that produces the final double precision result. By combining the partial products (P0, P1, P2, P3) through a structured addition network, the patent achieves standard-compliant double precision multiplication while reducing the total number of processing blocks required compared to conventional approaches that treat each multiplication operation independently
3Ease of manufacture
If conventional multiplication approaches are used, then implementation simplicity is maintained, but the number of processing blocks required increases
Solution Approach 1:
The patent divides the multiplication operation into segmented partial products that can be computed by smaller, simpler multiplier units. This segmentation allows the use of basic multiplier blocks rather than requiring complex large-scale multiplier circuits, simplifying the manufacturing and implementation while reducing processing block requirements
Solution Approach 2:
The patent transforms the problem from a single-dimension approach (one large multiplier block) to a multi-dimensional approach by organizing computations across multiple partial products and addition stages. This dimensional reorganization allows the system to achieve the same functional result using smaller, more numerous units arranged in a structured computational framework
Data Source
AI summary
Methods and systems for signal processing using processing blocks are provided. In one embodiment of the disclosure, there are provided a plurality of multiplier circuitries and control circuitry configured to multiply numbers AB and CD. The number AB includes components A and B, and the component A includes subcomponents AH and AL. The number CD includes components C and D, and the component C includes subcomponents CH and CL. The control circuitry is configured to compute a partial product AD based on multiplying D and AL using a first multiplier circuitry and based on multiplying D and AH the using a first multiplier module of a second multiplier circuitry. The control circuitry is also configured to compute a partial product CB based on B and CL using a third multiplier circuitry and based on multiplying B and the CH using a second multiplier module of the second multiplier circuitry.