DSP Decoupling Capacitor Layout for Low Digital Noise
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Solution Overview
Problem
Conventional digital signal processors generate significant digital noise due to high equivalent series resistance (ESR) and equivalent series inductance (ESL) in decoupling capacitors, leading to instability and increased power consumption, resulting in larger, more costly devices.
Innovation Solution
The use of solid electrolyte capacitors with reduced ESR and ESL, specifically designed for digital signal processors, to minimize noise and power consumption, allowing for a smaller, thinner, and more cost-effective design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the number of capacitors is increased to reduce digital noise, then the digital noise is reduced, but the board size and device complexity increase
Solution Approach 1:
The patent applies parameter changes by specifying precise ESR and ESL ranges for the solid electrolyte capacitor (ESR: 10-100 mΩ at 100 kHz, ESL: 50-200 pH at 1 GHz) to optimize noise reduction performance. This allows achieving effective digital noise suppression with fewer capacitors while maintaining stable voltage supply to the LSI.
2Reliability
If the ESR and ESL of the decoupling capacitor are decreased to ensure sufficient voltage, then the voltage stability is improved, but the capacitor performance requirements become more stringent and cost increases
Solution Approach 1:
The patent defines specific ESR and ESL parameter ranges that balance voltage stability with manufacturing feasibility. The ESR is set between 10-100 mΩ at 100 kHz and ESL between 50-200 pH at 1 GHz, providing optimal voltage suppression during LSI operation while remaining achievable with conventional solid electrolyte capacitor manufacturing processes.
3Speed
If the LSI operates at high frequency to process signals at high speed, then the signal processing speed is improved, but the power consumption increases and generates more digital noise
Solution Approach 1:
The solid electrolyte capacitor acts as an intermediary between the power supply and the LSI, suppressing high-frequency noise generated during high-speed operation. The capacitor's low ESL (50-200 pH at 1 GHz) enables it to effectively filter noise in the frequency range where the LSI operates, allowing high-speed signal processing with reduced noise emission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of solid electrolyte capacitors with controlled ESR and ESL significantly reduces digital noise, enabling a compact and economical digital signal processor with improved power management.
Implementation Method 1
The decoupling capacitor 28 supplies a current to the LSI 25 to stabilize the voltage supplied to the LSI 25
Implementation Method 2
The decoupling capacitor 28 has an equivalent series resistance (ESR) R and an equivalent series inductance (ESL) L. A current i flows from the decoupling capacitor 28 to the LSI 25. The decoupling capacitor 28 produces a dropping voltage V expressed by the following formula. V=R×i+L×di/dt.
Data Source
AI summary
A digital signal processor includes a component for processing a digital signal, a power line for supplying a power to the component, and a decoupling capacitor connected between the power line and a ground. The decoupling capacitor has an equivalent series resistance larger than zero and not larger than 25 mΩ at 100 kHz and an equivalent series inductance larger than zero and not larger than 800 pH at 500 MHz. This digital signal processor does not generate a lot of digital noise, and has a small, thin size.