Base Station DSP Clock Control for Power Reduction

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Solution Overview

Problem

In LTE mobile communication systems, the digital signal processing unit of an eNB frequently processes down-link signals without user traffic, leading to unnecessary power consumption due to continuous data processing for control information and reference signals.

Innovation Solution

The digital signal processing unit of the eNB tracks intervals where down-link signals are not allocated and controls the clock frequency to a lower level, reducing power consumption by gating the clock signal when no signal is present.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the digital signal processing unit continuously processes down-link signals including control information and reference signals, then the signal transmission function is maintained, but power consumption increases unnecessarily during intervals when user traffic is not allocated

Engineering Contradiction:
Improvesignal transmission functionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The clock frequency of the digital signal processing unit is made dynamic rather than fixed. The system switches between a first clock frequency (higher) when user traffic is allocated and a second clock frequency (lower) when user traffic is not allocated, allowing the processing unit to adapt its operational characteristics to match actual workload requirements while maintaining signal transmission capability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements periodic monitoring of resource block allocation status and periodically switches clock frequencies based on whether user traffic is allocated. This periodic action allows the system to maintain full processing capability when needed while reducing power consumption during idle intervals, creating a rhythm of high and low power states that matches traffic patterns

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If the clock frequency is reduced to lower power consumption levels, then energy efficiency improves, but the ability to process signals quickly when user traffic arrives may be degraded

Engineering Contradiction:
Improvepower consumptionVSAvoidsignal processing speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The system prepares for rapid response by maintaining the digital signal processing unit in a low-power state with reduced clock frequency during idle periods, while keeping the capability to quickly switch to a higher clock frequency when user traffic is detected. This preliminary preparation allows the system to be energy-efficient during idle times while retaining the ability to process signals at full speed when needed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The clock frequency parameter is changed based on operational conditions. The system transitions between two distinct frequency states: a first frequency that provides full processing speed when user traffic is allocated, and a second frequency that reduces power consumption during idle intervals. This parameter change allows the system to optimize between speed and energy efficiency dynamically

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3275144B1Digital signal processing device of base station and method for processing data thereof
Publication Date: 2023.04.26 SAMSUNG ELECTRONICS CO LTD
  • EP3275144B1 patent drawingFigure 1
  • EP3275144B1 patent drawingFigure 2~3
  • EP3275144B1 patent drawingFigure 4

AI summary

A digital signal processing device of a base station configured to process down-link signals in a wireless communication system employing orthogonal frequency division multiple access (OFDMA) and a method of processing data in the device are provided. The device includes a clock controller configured to monitor whether a signal is allocated to an input and control a frequency of clocks to have a first or second characteristic based on the monitored result, and a data processor configured to process the input, and synchronize with the clock controlled by the clock controller.