DSP Clock Synchronization via DMA Buffer Monitoring

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Solution Overview

Problem

Existing solutions for synchronizing a digital signal processor (DSP) with a network to maintain high-quality low-latency audio introduce unacceptable latency and are costly.

Innovation Solution

A system that synchronizes the local audio processing clock rate of a DSP with the network audio clock rate using an adjustable clock synthesizer, where the DSP generates events associated with its local clock rate and adjusts it based on monitored events to match the network clock rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If asynchronous sample rate converters (ASRCs) are used to synchronize the DSP to the network, then synchronization is achieved, but latency becomes unacceptable and cost increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidaudio latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the clock synchronization function from the data processing path by using a separate DMA channel to monitor buffer pointer positions independently. This allows synchronization information to be obtained without routing audio data through complex ASRC hardware, thereby reducing latency while maintaining synchronization accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary mechanism - the DMA buffer pointer monitoring system - that mediates between the network clock and DSP clock. By monitoring pointer positions in the buffer and using these positions to adjust the DSP clock rate, the system achieves synchronization without the latency introduced by direct ASRC conversion paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If asynchronous sample rate converters (ASRCs) are used to synchronize the DSP to the network, then synchronization is achieved, but device cost increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidhardware cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces expensive ASRC hardware with a software-based synchronization method using standard DSP components and DMA buffers. The buffer pointer positions serve as temporary, disposable markers for clock rate calculation, eliminating the need for costly dedicated ASRC circuitry while achieving the same synchronization function.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent substitutes physical ASRC hardware with a software-based clock adjustment mechanism. Instead of using dedicated conversion hardware, the system uses software to monitor buffer pointers and adjust the DSP clock rate, replacing complex mechanical/electrical synchronization hardware with simpler computational methods.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Loss of time

If the DSP clock rate is adjusted based on buffer pointer monitoring, then latency and jitter are reduced, but the system complexity increases

Engineering Contradiction:
Improveaudio latencyVSAvoidsoftware complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent makes the existing DMA buffer structure serve multiple functions: it continues to transfer audio data while simultaneously providing synchronization information through its pointer positions. This multi-functionality allows the system to achieve clock synchronization without adding separate dedicated hardware or complex software modules, as the buffer pointers serve dual purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a feedback mechanism where the DSP continuously monitors buffer pointer positions and adjusts its clock rate based on the observed data flow rate. This closed-loop feedback allows the system to automatically compensate for clock rate differences between the network and DSP, reducing latency and jitter without requiring complex manual configuration or additional hardware.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4348886B1Digital signal processor/network synchronization for processing audio data
Publication Date: 2025.05.14 BOSE CORP
  • EP4348886B1 patent drawingFigure 1
  • EP4348886B1 patent drawingFigure 2
  • EP4348886B1 patent drawingFigure 3

AI summary

A system for synchronizing a local audio processing clock rate of a digital signal processor (DSP) to an audio clock rate of a network to which the DSP is connected. The system includes an adjustable clock synthesizer that is configured to establish the local audio processing clock rate of the DSP. The DSP is configured to generate events that are associated with the local audio processing clock rate of the DSP. The DSP is further configured to monitor the generated events over time and based on the monitored events cause the adjustable clock synthesizer to adjust the local audio processing clock rate of the DSP to better match the network audio clock rate.