DSP Conditional Negation Instruction for LLR Pipelining
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Solution Overview
Problem
Traditional digital signal processing (DSP) implementations face inefficiencies in performing conditional negation of log-likelihood ratio (LLR) values due to the need for 'if' statements, which disrupt pipelining and limit parallel processing, especially in high-demand applications like 4G mobile telecommunication systems.
Innovation Solution
An integrated circuit device and method that includes a dedicated conditional negation instruction for DSP devices, allowing conditional negation operations to be performed directly within data execution units based on conditional bit values stored in data registers, eliminating the need for 'if' statements and enabling parallel execution of multiple operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 'if' statements are used to perform conditional negation of LLR values, then the operation can be performed correctly, but the pipelined architecture benefits are lost and throughput is significantly reduced
Solution Approach 1:
The patent extracts the conditional logic from traditional 'if' statements and implements it through a dedicated conditional negation instruction with a condition code register. This separates the conditional evaluation (performed in hardware) from the execution flow, allowing the pipeline to continue without interruption while still achieving the required conditional negation functionality.
Solution Approach 2:
The patent introduces a condition code register as an intermediary between the conditional bit and the negation operation. This register holds the condition value and enables the execution unit to perform conditional negation without requiring flow control instructions, thus maintaining pipeline integrity while achieving the desired conditional behavior.
2Productivity
If pipelined architecture is implemented to improve throughput, then cycle per instruction is reduced, but conditional negation operations cannot be performed efficiently due to flow changes
Solution Approach 1:
The patent merges the conditional evaluation and the negation operation into a single unified instruction (conditional negation instruction). This combination allows the operation to be executed atomically within the pipeline without requiring separate condition checking and flow control instructions, thereby maintaining both high throughput and ease of conditional operation execution.
3Device complexity
If limited predicate bits are available for conditional operations, then the device complexity is constrained, but the ability to perform multiple conditional negations per cycle is limited
Solution Approach 1:
The patent transitions from using multiple separate predicate bits to using a single condition code register that can be reused across multiple operations. This dimensional change from parallel predicate bits to a temporal reuse model allows unlimited conditional negation operations per cycle while maintaining constant device complexity, as the same condition code register serves multiple operations sequentially within the pipeline.
Data Source
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AI summary
An integrated circuit device (105) comprising at least one digital signal processor (DSP) module (100), the at least one DSP module (100) comprising a first data register and at least one further data register (140) and at least one data execution unit (DEU) module (120) arranged to execute operations on target data stored within the first data register and the at least one further data register (140). The at least one DEU module (120) is arranged, upon receipt of a conditional negation instruction (210), to retrieve at least one conditional bit value (225, 325) from the first data register (220), and conditionally perform negation of target data within the at least one further data register (230) according to the at least one retrieved conditional bit value (225, 325).