DSP Data Conversion Architecture for Smaller RAM Footprint
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Solution Overview
Problem
The memory area of dedicated Digital Signal Processors (DSPs) is excessively large, leading to increased cost and area occupation, particularly due to the traditional method of data interaction and conversion which results in a RAM memory area that is N/N' times larger, where N' is the bit width of the input data.
Innovation Solution
A device and method for data interaction and conversion within a dedicated DSP, where first mode data is converted into second mode data with different bit width or format, and then further converted into third mode data for computation, allowing the second mode data to be stored, thereby reducing the memory area occupied by the data storage unit and the overall DSP area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is converted from N' bits to N bits using traditional conversion method, then data interaction between hardware unit and DSP is achieved, but the RAM memory area increases to N/N' times
Solution Approach 1:
The patent segments the data conversion process into multiple stages: first converting N' bit data to intermediate representation, then to N bit data for DSP processing. This segmentation allows using smaller memory units at different stages rather than requiring full N-bit memory throughout, reducing overall RAM area while maintaining data interaction capability.
Solution Approach 2:
The patent implements nested data structures where smaller bit-width data units are nested within larger bit-width memory structures. The N' bit data from hardware units is processed through intermediate buffers before being stored in N-bit RAM, creating a nested memory hierarchy that reduces the total memory area required.
2Quantity of substance
If the RAM memory area is increased to N/N' times, then the data storage capacity is sufficient, but the overall DSP area and cost increase
Solution Approach 1:
The patent applies local quality by using different memory configurations for different functional areas within the DSP. Instead of uniformly increasing all memory to N-bit width, it selectively applies N-bit memory only where required for DSP operations, while using N' bit memory for hardware unit interfaces, thereby maintaining storage capacity while reducing overall area.
Solution Approach 2:
The patent introduces a temporal dimension to data storage by using buffer registers and shift registers that process data in streams rather than requiring all data to be simultaneously stored in large static memory. This dimensional change from spatial to temporal storage reduces the area required for data storage capacity.
Data Source
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AI summary
A device for data interaction and conversion includes a hardware unit (410) and a dedicated DSP unit (420). The hardware unit (410) is arranged to exchange first mode data with the dedicated DSP unit (420). The dedicated DSP unit (420) is arranged to: receive first mode data from the hardware unit (410), convert the first mode data into second mode data which has different at least one of bit width and format from the first mode data, and convert the second mode data into third mode data which has different at least one of bit width and format from the second mode data, and compute the third mode data; or is arranged to: convert third mode data returned after computation into second mode data which has different at least one of bit width and format from the third mode data; and convert the second mode data into first mode data which has different at least one of bit width and format from the second mode data, and send the first mode data to the hardware unit (410). Also a DSP, a method for data interaction and conversion, and a storage medium are provided.