Configurable Digital Signal Processing Data Transfer via Multi-threaded Control
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Solution Overview
Problem
Digital signal processing systems face challenges in handling real-time data due to varying requirements across different digital television and radio standards, necessitating different hardware configurations for each standard, which limits configurability and increases complexity.
Innovation Solution
A configurable digital signal processing system utilizing a multi-threaded processor to control data transfer between fixed function accelerators and memory, allowing for dynamic reconfiguration without hardwiring, enabling efficient processing of diverse real-time data standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated inter-connected hardware peripherals are used to meet specific real-time data requirements, then processing speed and efficiency are improved, but device complexity and lack of configurability increase
Solution Approach 1:
The patent implements a universal data transfer system where a single configurable interconnection network can dynamically route data between different hardware peripherals and memory devices. Instead of dedicated hardwired connections for each processing path, the system uses a multi-functional switching fabric that can be programmed to create different data flow topologies, enabling the same hardware to efficiently process multiple real-time data standards with varying requirements.
Solution Approach 2:
The system employs dynamic reconfiguration capabilities where the interconnection network's routing paths and data flow configurations can be changed in real-time or between processing tasks. This allows the hardware peripheral connections to be dynamically adjusted to match the specific requirements of different digital television and radio standards, providing both high-speed processing and adaptability.
2Productivity
If different digital signal processing systems are constructed for each real-time data type, then processing efficiency for specific standards is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent describes a universal data transfer system that can be manufactured as a single standardized platform capable of supporting multiple digital television and radio standards. The configurable interconnection network and programmable controllers enable this single system design to be efficiently manufactured and deployed, eliminating the need to produce separate specialized systems for each standard while maintaining high processing efficiency for all supported formats.
3Reliability
If hardwired connections are used between hardware peripherals, then data transfer reliability is improved, but adaptability to different data standards decreases
Solution Approach 1:
The patent introduces a configurable interconnection network as an intermediary layer between hardware peripherals and memory devices. This mediator provides reliable, controlled data transfer through programmable routing and switching functions, replacing direct hardwired connections while maintaining transfer reliability through error checking, flow control, and deterministic routing capabilities built into the switching fabric.
Data Source
AI summary
A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.