DSP DRAM Memory Architecture Without Refresh Operations
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Solution Overview
Problem
Digital signal processors using DRAM require frequent refresh operations due to charge leakage, which consumes significant electricity, while SRAM does not need refresh but has larger memory cells, and existing technologies struggle to optimize memory access patterns for efficient data input/output.
Innovation Solution
A digital signal processor utilizing a DRAM with parasitic capacitors and dual ports, allowing data to be read and recorded before retention time expires, thereby omitting the need for refresh operations and reducing memory cell size and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If DRAM is used for embedded memory in DSP, then memory cell area is reduced compared to SRAM, but refresh operations are required which consume significant electricity
Solution Approach 1:
The patent applies preliminary action by performing read operations before the retention time of DRAM cells expires. The memory controller monitors retention time and schedules read operations to complete before charge leakage causes data loss, eliminating the need for periodic refresh operations while maintaining data integrity throughout the processing cycle
Solution Approach 2:
The system uses the natural retention time characteristic of DRAM cells to determine when reads must occur, allowing the memory subsystem to self-regulate its operation without external refresh control. The retention time itself becomes the governing parameter that dictates the timing of all memory operations
2Loss of energy
If SRAM is used for embedded memory in DSP, then refresh operations are not needed, but memory cell area becomes significantly larger
Solution Approach 1:
The patent schedules all read operations to occur before DRAM retention time expires, performing the necessary data retrieval in advance before charge leakage becomes problematic. This preliminary timing action eliminates the need for subsequent refresh operations entirely
3Duration of action of stationary object
If DRAM is used with traditional refresh operations, then data retention is maintained, but power consumption increases significantly
Solution Approach 1:
The memory controller performs read operations before retention time expires, ensuring data is retrieved while still valid. This preliminary timing action prevents charge leakage from causing data loss, eliminating the need for refresh operations that would consume additional power
Solution Approach 2:
The system uses retention time as a feedback parameter to control memory operations. The retention time characteristic of DRAM cells provides feedback that dictates when reads must occur, creating a self-regulating system that adapts to the physical properties of the memory medium
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of refresh operations, smaller memory cell area, and increased area efficiency, while maintaining data integrity by reading input data before retention time, thus reducing power consumption and enhancing memory bandwidth.
Implementation Method 1
a DRAM including multiple memory cells configured to store data in a parasitic capacitor
Data Source
AI summary
The digital signal processor includes a DRAM including multiple memory cells configured to store data in a parasitic capacitor and a core logic configured to perform an operation of recording, reading, or updating data in the DRAM on the basis of a predetermined digital signal processing architecture. The core logic: records input data in a memory cell of the DRAM; reads the recorded input data before a retention time passes; and externally outputs the data or stores the data in another memory cell of the DRAM.