DSP Engine Implicit Mixed Operand Multiplier
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Solution Overview
Problem
Existing digital signal processor (DSP) engines face challenges in performing high-precision mathematical operations efficiently, particularly with 32-bit multiplications, which require significant processing time and additional hardware, increasing cost and complexity.
Innovation Solution
A DSP processor with a configurable multiplier unit that can operate in signed, unsigned, or mixed sign mode, allowing for automatic selection based on operand locations, enabling 32-bit multiplications without dedicated hardware by splitting operands into 16-bit parts and performing multiple multiplications with appropriate shifting and adding, thus maintaining processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dedicated 32-bit multipliers are added to perform high-precision calculations, then calculation precision is improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent segments 32-bit multiplication into multiple 16-bit operations. The multiplier unit processes operands in 16-bit chunks, performing separate multiplications for different sign combinations (signed/signed, unsigned/unsigned, signed/unsigned, unsigned/signed) and combining the results through shifting and adding. This segmentation allows existing 16-bit DSP hardware to achieve 32-bit precision without requiring dedicated 32-bit multiplier hardware.
Solution Approach 2:
The patent makes the existing 16-bit multiplier unit universal by enabling it to perform multiple functions: 16-bit signed multiplication, 16-bit unsigned multiplication, and 32-bit multiplication through combination of multiple 16-bit operations. The multiplier unit is configured to handle different operand types and precision requirements using the same hardware resource, eliminating the need for separate dedicated 32-bit multiplier hardware.
2Measurement precision
If higher precision multiplications are performed using larger accumulators, then calculation precision is improved, but processing speed decreases significantly
Solution Approach 1:
The patent segments the multiplication process into multiple parallel 16-bit operations that can be executed efficiently. By breaking down 32-bit multiplication into smaller 16-bit chunks with appropriate shifting and adding, the system maintains processing speed while achieving higher precision, avoiding the bottleneck of using large accumulators for single operations.
Solution Approach 2:
The patent dynamically configures the multiplier unit to operate in different modes (signed/signed, unsigned/unsigned, signed/unsigned, unsigned/signed) based on the input operands. This dynamic adaptation allows the system to optimize processing speed for each specific calculation type while maintaining the capability for high-precision 32-bit operations when needed.
3Measurement precision
If multiple high precision multiplications are performed sequentially, then calculation precision is improved, but processing time increases substantially
Solution Approach 1:
The patent segments 32-bit multiplication into multiple 16-bit operations that can be performed more efficiently. By using the existing 16-bit multiplier unit multiple times with appropriate shifting and adding, the system reduces the time required compared to using a single slow 32-bit multiplier or large accumulator approach, while still achieving the necessary precision for operations like FFT.
4Adaptability or versatility
If new instructions are added to operate additional hardware, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent enables the existing 16-bit multiplier unit to perform multiple functions (16-bit signed, 16-bit unsigned, and 32-bit multiplication) without requiring new instructions. The same hardware resource is configured differently based on the operation type, maintaining compatibility with existing instruction sets while adding versatility to handle various precision requirements.
Data Source
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AI summary
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.