DSP Error Detection Coding for Low-Latency Data Packets
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Cyclic redundancy check (CRC) codes used in communications systems are inefficient for high-data-rate transmissions due to increased latency and overhead, especially in modern digital signal processor (DSP) technologies like software-defined radios, where the time for CRC processing decreases, leading to loading and latency issues.
Innovation Solution
A fast error detection (FED) mechanism using a digital signal processor (DSP) with a multiply/accumulate (MAC) unit processes data packets by multiplying each data word with values from a pre-computed distance table, reducing the sum to desired bit lengths for error detection, and appending these as FED codes to the data packet, similar to standard CRC techniques but more computationally efficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard CRC codes are used for error detection in high-data-rate transmissions, then error detection capability is maintained, but processing latency and computational overhead increase
Solution Approach 1:
The patent changes the computational parameters of error detection by replacing traditional CRC polynomial division with a dot-product-based calculation using pre-computed distance tables. This parameter change transforms the operation from sequential bit processing to parallel word-level operations, significantly reducing processing latency while maintaining error detection capability through optimized distance metrics
Solution Approach 2:
The patent applies preliminary action by pre-computing distance tables during system initialization or offline processing. These tables contain pre-calculated distance metrics for all possible data word combinations, allowing the receiver to perform rapid error detection through simple table lookups and dot products without performing complex calculations in real-time during data transmission
2Reliability
If CRC bits are appended to each data packet for error detection, then transmission reliability is improved, but overhead increases significantly for short burst transmissions
Solution Approach 1:
The patent changes the parameter of error detection computation from traditional CRC methods requiring multiple bits to an optimized dot-product approach that achieves equivalent or superior error detection with fewer bits. By utilizing pre-computed distance tables and efficient accumulation algorithms, the system maintains high reliability while reducing the number of check bits required, thereby decreasing transmission overhead
3Adaptability or versatility
If feedback shift-register architectures are used to generate CRC codes, then standardization and compatibility are achieved, but processing speed decreases due to sequential operation
Solution Approach 1:
The patent substitutes the mechanical feedback shift-register architecture with a digital signal processing approach using dedicated MAC units and pre-computed lookup tables. This replacement transforms the sequential mechanical shifting and XOR operations into parallel digital computations, achieving both standardization through compatible error detection performance and dramatically improved processing speed suitable for high-data-rate transmissions
Data Source
AI summary
A system apparatus and method generates a communications signal having an error detection mechanism. A circuit generates a data packet. An encoder multiplies and accumulates data words with values in a distance table containing non-repeated n-bit multipliers having “m” number of one bits that are set to obtain accumulated sum bits and appends the accumulated sum bits to the data packet as an error detection code to form a communications signal to be transmitted.