Flexible DSP Filter Circuit Without Pre-Adders for Complex Multiplication
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Solution Overview
Problem
In deep submicron integrated circuits, pre-adders required for arithmetic operations in DSP blocks occupy valuable die area and increase power consumption due to the need for a register stage between adders and multipliers, disrupting timing closure and area efficiency.
Innovation Solution
Replacing pre-adders with additional multipliers in DSP blocks to perform addition operations, allowing for the same arithmetic functionality with reduced area usage and lower latency, while also enabling complex multiplication capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If pre-adders are used in DSP blocks for symmetric FIR filters, then arithmetic functionality is improved, but die area and power consumption increase due to required register stages
Solution Approach 1:
The patent makes multipliers universal by enabling them to perform both multiplication and addition operations. The same multiplier circuitry that would normally only multiply can now also function as an adder through selective activation, eliminating the need for separate pre-adder circuits and their associated register stages, thus reducing die area while maintaining arithmetic functionality
Solution Approach 2:
The patent merges the functions of pre-adders and multipliers into a single integrated circuit block. By combining the addition capability within the multiplier structure itself, the design eliminates separate adder components and their timing-critical register stages, achieving both area reduction and timing improvement
2Ease of operation
If pre-adders are used in DSP blocks, then arithmetic operations can be performed, but timing closure becomes difficult due to additional register stages
Solution Approach 1:
The patent merges addition and multiplication operations into a single unified circuit stage. By performing both operations in the same clock cycle without intermediate register stages, the design achieves better timing closure while maintaining full arithmetic operation capability
3Area of stationary object
If additional multipliers are used to replace pre-adders, then area efficiency improves, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by making multipliers universal - each multiplier can be dynamically configured to perform either multiplication or addition based on operational requirements. This eliminates the need for separate dedicated adder circuits and their control logic, simplifying the overall device architecture while improving area efficiency
Data Source
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AI summary
Integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. An integrated circuit may include programmable logic circuitry and digital signal processor (DSP) blocks. The DSP blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. The first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. The second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.