DSP Filter Configuration Using Common-Coefficient Pre-Adders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuits are inefficient in implementing arithmetic operations for digital signal processing (DSP) applications due to inefficient layouts and resource utilization in DSP blocks, leading to suboptimal circuit performance and power dissipation.
Innovation Solution
A method and circuit configuration that transforms a high-level filter design into a symmetric transpose convolution filter using a processing block with a pre-adder circuit, optimizing the placement of taps with common coefficients to minimize DSP stages and reduce resource requirements, by providing the sum or difference of taps as inputs to a multiplier, thereby eliminating the need for logic outside the DSP blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional DSP blocks are used with standard filter implementation, then the circuit can perform basic DSP functions, but the layout efficiency and resource utilization are poor
Solution Approach 1:
The patent combines multiple filter taps with common coefficients into a single DSP block by summing the taps externally and providing the sum as one input to the multiplier. This merging approach reduces the total number of DSP blocks required while maintaining the same filtering function, thereby improving layout efficiency and reducing circuit resource usage.
Solution Approach 2:
The patent creates a universal DSP block configuration that can handle both standard and symmetric filter implementations. By providing flexibility in how taps are connected and processed, the same DSP block structure can be used for various filter types, improving resource utilization and manufacturing efficiency.
2Reliability
If more DSP stages are used to implement the filter, then the filtering function is more complete, but the power dissipation and resource requirements increase
Solution Approach 1:
By merging multiple taps that share common coefficients into a single processing unit, the patent reduces the total number of DSP stages required. This combination maintains complete filtering functionality while reducing power dissipation by eliminating redundant computational stages.
Solution Approach 2:
The patent performs preliminary summation of taps with common coefficients before they reach the multiplier stage. This pre-processing step reduces the computational load on subsequent DSP stages, thereby reducing overall power consumption while maintaining filtering completeness.
3Ease of manufacture
If standard filter configuration is used, then the design is simple to implement, but the resource utilization and efficiency are suboptimal
Solution Approach 1:
The patent maintains design simplicity by using standard DSP block components while improving resource utilization through clever configuration. By combining multiple taps externally and using the sum as a single input, the design remains straightforward but achieves superior resource efficiency.
Solution Approach 2:
The patent changes the configuration parameters of the DSP blocks to optimize resource utilization. By adjusting how taps are connected and processed, the same basic components achieve higher efficiency without complicating the overall design approach.
Data Source
AI summary
According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzing coefficients of the filter; and transforming the filter of the high level design to a filter using a processing block of the circuit configured to accommodate a common coefficient, wherein the processing block is coupled to receive taps associated with the common coefficient. A computer program product and a circuit for configuring a filter in a circuit to be implemented in an integrated circuit are also disclosed.