Digital Signal Processor Floating-Point CORDIC Processing
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Solution Overview
Problem
Existing digital signal processors face inefficiencies in processing the CORDIC algorithm, particularly due to the need for data format conversion between fixed and floating-point formats, which slows down processing and increases processing time.
Innovation Solution
A digital signal processor is designed to implement the CORDIC algorithm directly in a floating-point format, using electronic circuits that perform divisions by integer powers of 2 through exponent manipulation, eliminating the need for conventional dividers and allowing for faster iterations by reducing the critical path and silicon space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional dividers are used to perform divisions by integer powers of 2 in fixed-point format, then the processing is more accurate, but the processing time increases and the critical path lengthens
Solution Approach 1:
The patent changes the data representation parameter from fixed-point to floating-point format. This enables divisions by integer powers of 2 to be performed by simply adjusting the exponent field rather than using complex division circuits, dramatically reducing the critical path and processing time while maintaining numerical precision through the floating-point representation's ability to track magnitude separately from mantissa.
Solution Approach 2:
The patent replaces the mechanical/divisional operation with a simpler exponential adjustment operation. Instead of using conventional dividers that perform actual division operations, the system uses floating-point exponent manipulation to achieve the same mathematical effect of division by powers of 2, substituting a complex mechanical process with a simpler algebraic operation.
2Adaptability or versatility
If data format conversion between fixed-point and floating-point is performed, then the processor can handle floating-point data, but the processing time increases due to format conversion overhead
Solution Approach 1:
The patent makes the CORDIC processor universally compatible with floating-point data formats by designing the entire processing pipeline to natively operate in floating-point. This eliminates the need for format conversion interfaces or translation layers, allowing the processor to directly accept and produce floating-point results without time-consuming format changes.
Solution Approach 2:
The patent extracts and eliminates the format conversion step from the processing pipeline. By removing the intermediate conversion stage between fixed-point and floating-point formats, the system achieves direct floating-point processing, thereby eliminating the time loss associated with format conversion while maintaining full floating-point compatibility.
3Measurement precision
If conventional dividers are used in the processing circuit, then the division operations are more precise, but the silicon space required increases
Solution Approach 1:
The patent changes the operational parameter from using dedicated division circuits to using floating-point exponent arithmetic. This parameter change allows the system to achieve precise division by powers of 2 through simple exponent subtraction operations rather than requiring large-area divider circuits, thereby reducing silicon space while maintaining division precision through the mathematical properties of floating-point representation.
Solution Approach 2:
The patent substitutes complex mechanical division circuits with simpler exponential adjustment mechanisms. Instead of implementing physical divider circuits that occupy significant silicon area, the system uses floating-point exponent manipulation to achieve the same division effect, replacing a space-intensive mechanical approach with a compact algebraic approach.
Data Source
AI summary
A digital signal processor according to an embodiment comprises a processing stage. The processing stage is configured to receive Cartesian coordinates of a vector in a floating point format and to output polar coordinates of the vector in a floating point format. The processing stage comprises a first electronic circuit configured to iteratively implement, timed by a clock signal, a CORDIC algorithm in a floating point format.