DSP Block Floorplan With Cascaded Interconnect for Fabric Bottlenecks
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Solution Overview
Problem
The increasing demand for real-time, concurrent arithmetic operations in digital signal processing (DSP) applications exceeds the capabilities of traditional DSP chips and Programmable Logic Devices (PLDs), as the latter face bottlenecks due to the limitations of multiple DSP elements programmed in the PLD fabric.
Innovation Solution
A physical IC floorplan for a DSP block is designed, featuring cascaded DSP elements with programmable interconnects, multiplexers, and an arithmetic logic unit, optimized for improved performance by configuring the interconnects and logic elements to enhance arithmetic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP elements are programmed in the PLD fabric, then concurrent DSP operations are enabled, but the fabric becomes a bottleneck limiting further performance improvement
Solution Approach 1:
The PLD is segmented into multiple DSP blocks, each containing dedicated DSP elements with specialized interconnect structures. This segmentation allows concurrent operations within each block while reducing the burden on the global fabric, as elements can communicate locally within their block before accessing the fabric for external data.
Solution Approach 2:
Local interconnect structures act as intermediaries between DSP elements within a block and the global fabric. These intermediaries handle internal data routing and preprocessing, reducing traffic on the main fabric and eliminating it as a bottleneck for concurrent operations.
2Productivity
If more DSP microprocessors are added to perform DSP applications, then arithmetic operations per second increase, but the same disadvantage of general-purpose microprocessors applies
Solution Approach 1:
Multiple DSP elements are merged into integrated DSP blocks with shared local resources (registers, interconnect, arithmetic logic units). This merging achieves high arithmetic throughput while reducing overall system complexity compared to using separate general-purpose microprocessors for each DSP function.
Solution Approach 2:
The DSP elements are designed with programmable characteristics, allowing dynamic reconfiguration of their function and interconnect structure. This dynamics enables the same hardware to adapt to different DSP algorithms, achieving high performance without the complexity of multiple dedicated processors.
3Device complexity
If a single DSP microprocessor is used, then the device is simple, but it cannot meet the increasing demand for real-time concurrent arithmetic operations
Solution Approach 1:
DSP elements are nested within DSP blocks, which are themselves integrated into the PLD fabric. This nesting provides a hierarchical structure where simple individual elements combine to form more complex functional blocks, achieving high concurrent operation capability while maintaining relative simplicity at each level.
Data Source
AI summary
A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.