DSP Global Local Interconnect Architecture
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Solution Overview
Problem
Existing DSP processor architectures face limitations in data transfer efficiency and flexibility, particularly with hardware accelerator cores, which hinder their performance and adaptiveness in complex, data-rich environments.
Innovation Solution
A digital signal processor (DSP) with a global and local interconnect architecture, featuring multiple DSP hardware accelerator cores with user-configurable DSP modules and memory-mapped data transfers, enabling efficient data transfer and flexible operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a global interconnect is used for data transfer between all DSP hardware accelerator cores, then data transfer coverage is improved, but data transfer latency increases and bandwidth is consumed
Solution Approach 1:
The interconnect architecture is segmented into two distinct networks: a global interconnect for long-distance communication between non-adjacent cores, and a local interconnect for short-distance communication between adjacent cores. This segmentation allows data to be routed through the appropriate network based on destination, reducing unnecessary traversal through the global interconnect and lowering latency for local operations.
Solution Approach 2:
The local interconnect acts as an intermediary for adjacent core communication, handling data transfers that would otherwise require routing through the global interconnect. This intermediary layer reduces the burden on the global interconnect and provides a faster, more direct path for local data exchanges.
2Speed
If a local interconnect is used for data transfer between adjacent DSP hardware accelerator cores, then data transfer speed is improved, but interconnect complexity increases
Solution Approach 1:
The local interconnect is designed with multi-functionality, serving both as a high-speed data transfer path between adjacent cores and as a routing intermediary for the global interconnect. This universal design justifies the added complexity by providing multiple benefits from a single architectural addition.
3Power
If hardware accelerator cores are added to improve DSP processing capability, then processing power is improved, but data transfer efficiency deteriorates
Solution Approach 1:
The interconnect architecture is segmented to provide dedicated local interconnects for adjacent core communication, enabling high-speed data transfer that keeps pace with the increased processing power of multiple hardware accelerator cores. This prevents the data transfer bottleneck that would otherwise limit the effectiveness of added processing capability.
4Manufacturing precision
If fixed-function DSP hardware accelerator cores are used, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The DSP hardware accelerator cores incorporate reconfigurable logic that allows their functionality to be dynamically changed after manufacturing. This enables the same physical core to be programmed for different DSP operations, combining the precision of fixed-function implementation with the flexibility of reconfigurability.
Solution Approach 2:
The cores utilize configurable parameters such as data width, clock frequency, and operational mode that can be adjusted through programming. This allows the same hardware structure to adapt to different performance requirements and application scenarios while maintaining manufacturing precision.
Data Source
AI summary
A digital signal processor (DSP) with a global and local interconnection architecture includes a plurality of DSP hardware accelerator cores each including at least one DSP module for performing a DSP operation. The DSP further includes a global interconnect for data transfer between non-adjacent ones of the DSP hardware accelerator cores and between the DSP hardware accelerator cores and processing elements external to the DSP hardware accelerator cores. The DSP further includes a local stream interconnect associated with each of the DSP hardware accelerator cores for data transfer within each core and for data transfer between adjacent ones of the DSP hardware accelerator cores.