DSP Local Memory Permutation Architecture
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Solution Overview
Problem
Conventional digital signal processor architectures face performance constraints due to limited memory size and bandwidth, particularly in complex digital signal processing functions like DFTs and Kasumi cipher applications, where large data blocks require frequent memory access, leading to increased latency and reduced efficiency.
Innovation Solution
A programmable digital logic integrated circuit architecture with multiple memory resources and permutation circuitry, allowing for efficient random access and stack operations, and enabling simultaneous execution of multiple instructions across subclusters connected via a crossbar switch, with local memory banks that can be accessed as random access or stack memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in global data memory, then memory capacity is sufficient for large data blocks, but memory access latency increases and bandwidth is shared
Solution Approach 1:
The memory system is segmented into local memory resources associated with each subcluster and global data memory. Local memory provides fast access for frequently used data while global memory provides large capacity for entire data blocks, resolving the contradiction between speed and capacity through hierarchical segmentation.
Solution Approach 2:
Local memory resources act as intermediaries between functional units and global data memory. They buffer data locally to reduce access latency to global memory, providing a mediation layer that combines the benefits of fast local access with large global capacity.
2Quantity of substance
If data is accessed from global data memory, then large data blocks can be stored, but bandwidth is shared leading to reduced access efficiency
Solution Approach 1:
Memory bandwidth is segmented by providing dedicated local memory resources to each subcluster. This segmentation allows multiple subclusters to access their own local memory simultaneously without contending for global memory bandwidth, maintaining high productivity while supporting large data blocks through hierarchical storage.
Solution Approach 2:
The memory architecture adds a spatial dimension by distributing local memory resources across multiple subclusters. This dimensional expansion allows parallel access paths, increasing overall bandwidth capacity while maintaining efficient access to large data blocks through the hierarchical structure.
3Productivity
If contiguous memory addresses are accessed, then memory access is efficient, but permuted access patterns required by some DSP operations reduce efficiency
Solution Approach 1:
The memory address translation mechanism is made dynamic by introducing permutation registers that can be configured for different access patterns. The system adapts between contiguous and permuted access modes based on operational requirements, maintaining high productivity for both access types through configurable address translation.
Solution Approach 2:
The address mapping parameters are changed dynamically through permutation registers. By modifying the address translation parameters based on the required access pattern, the system maintains efficient memory access for both contiguous and permuted patterns, adapting to different DSP operation requirements.
Data Source
AI summary
A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.