DSP Modulo Address Generation for Matrix Column Access
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Solution Overview
Problem
Existing address generation units for digital signal processors are inefficient in generating address sequences for accessing matrix elements column by column, requiring additional cycles and complex hardware or programming to correctly address all elements, especially the last element in a matrix.
Innovation Solution
A device with an adder, subtractor, and multiplexer that generates addresses by adding an increment and subtracting a modulo, with a modified multiplexer condition to select the first address if the second address is lower than or equal to zero, allowing efficient column-wise addressing with minimal additional resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a standard modulo address generation unit is used, then linear addressing is efficient, but column-wise addressing requires additional cycles and complex hardware
Solution Approach 1:
The invention changes the selection criterion parameter from 'second address < 0' to 'second address ≤ 0'. This parameter modification enables the same hardware to correctly generate column-wise address sequences without requiring additional complex logic or multiple cycles, thereby resolving the contradiction between addressing efficiency and hardware complexity
2Reliability
If a standard modulo address generation unit is used, then simple addressing works correctly, but the last element in column-wise addressing cannot be directly addressed
Solution Approach 1:
By modifying the multiplexer selection condition to include equality ('≤ 0' instead of '< 0'), the invention ensures that when the second address equals zero (which occurs at the last element in column-wise addressing), the first address is selected. This guarantees correct addressing of the last element while maintaining single-cycle operation, thus resolving the contradiction between reliability and productivity
3Reliability
If additional hardware is added to support column-wise addressing, then all elements can be addressed correctly, but implementation complexity increases
Solution Approach 1:
The invention avoids adding any hardware by simply changing the software parameter (the comparison condition in the multiplexer control logic) from '< 0' to '≤ 0'. This minimal change enables correct column-wise addressing of all elements including the last element, while keeping implementation complexity low and maintaining ease of manufacture
Data Source
AI summary
A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31) and a modulo value (33). The next address (36) is generated based on these inputs as follows. An adder (22) generates a first address (32) by adding the input address (30) and the increment (31) and a second address (34) is generated by subtracting the modulo (33) from the first address (32) by means of the subtractor (23). The comparator (45) checks whether the second address is lower than or equal to zero and if so, the multiplexer (24) outputs the first address at its output (36). If the second address is higher than zero, the multiplexer (24) is controlled such that it outputs the second address (34). A further comparator (63) compares the input address (30) and the modulo (33). If the input address (30) is different from the modulo (33), the multiplexer (64) generates the next output address (66) by selecting the output (36) of the multiplexer (24) and if the input address (30) is equal to the modulo (33) the multiplexer (64) generates the next output address (66) by selecting the constant value “0” (67) inputted at a second input of the multiplexer (64). This modulo arithmetic allows to directly and repeatedly access the elements of a matrix stored in a digital memory row by row in a direction of its columns.