DSP Megamodule Memory Architecture for Low-Latency Streaming
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Solution Overview
Problem
Modern digital signal processors face challenges such as increasing workloads, memory system latency, and limited bandwidth, which are exacerbated by the complexity of systems on a chip and the in-order nature of central processing units, leading to subpar performance and software integration issues.
Innovation Solution
The integration of streaming engines with vector support, scoreboarded loads, speculative loads, and software-directed prefetch, along with a credit-based bidirectional bus protocol, enhances memory system efficiency and coherence, allowing for improved bus utilization and data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bus width and clock rate are increased to improve bandwidth, then bandwidth is improved, but wire count and routing complexity increase
Solution Approach 1:
The patent divides the monolithic high-bandwidth bus into multiple lower-bandwidth virtual channels that can operate independently. This segmentation allows the system to achieve high aggregate bandwidth through parallelism rather than through a single wide bus, thereby reducing wire count and routing complexity while maintaining or improving overall bandwidth capacity.
2Speed
If pipelining is increased to achieve faster clock rates, then clock rate is improved, but latency increases
Solution Approach 1:
The patent implements speculative execution and prefetching mechanisms that perform actions before they are strictly needed. By predicting future memory access patterns and executing instructions speculatively, the system prepares data and results in advance, effectively hiding latency without requiring excessive pipelining stages that would increase clock rate requirements.
3Device complexity
If the CPU is made in-order to simplify control, then control complexity is reduced, but performance on streaming workloads deteriorates
Solution Approach 1:
The patent separates the control logic into distinct in-order and out-of-order execution paths. The in-order path handles control flow and maintains simplicity, while the out-of-order path handles data processing and memory operations, allowing aggressive optimization for streaming workloads without increasing overall control complexity.
Solution Approach 2:
The patent introduces a scoreboard mechanism as an intermediary between the in-order control logic and the execution units. This scoreboard tracks the status of operations and enables out-of-order completion while maintaining in-order issue, allowing the system to achieve high streaming performance without the full complexity of complete out-of-order execution.
4Quantity of substance
If cache line size is increased to improve memory efficiency, then memory efficiency is improved, but cache penalty for streaming workloads increases
Solution Approach 1:
The patent divides the cache into multiple smaller ways or sets that can be independently accessed. This segmentation allows the cache to efficiently handle streaming workloads by accessing specific segments rather than requiring full cache line transfers, reducing cache penalty while maintaining memory efficiency through coordinated access patterns.
Data Source
AI summary
Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.