DSP Processor MMU Segmentation for Parallel External Memory Fetching
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Solution Overview
Problem
Existing digital signal processors face inefficiencies in accessing external memory due to serial operations in memory management units, leading to increased maintenance costs and reduced system efficiency when multiple processors are integrated, and there is a risk of memory stomping.
Innovation Solution
Implementing separate memory management units for program and data ports in digital signal processors, allowing parallel fetching of instructions and data, and incorporating translation lookaside buffers (TLBs) to manage access addresses, which simplifies hardware design and supports parallel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a unified MMU is used for both program and data ports, then device complexity is reduced, but system efficiency deteriorates due to serial operations
Solution Approach 1:
The patent divides the unified MMU into separate program port MMU and data port MMU modules. Each MMU independently handles address translation for its respective port, enabling parallel operations. This segmentation resolves the contradiction by sacrificing some structural simplicity to achieve significant efficiency improvement through parallel processing.
2Device complexity
If multiple digital signal processors share off-chip memory space without individual allocation, then device complexity is reduced, but reliability deteriorates due to memory stomping risks
Solution Approach 1:
The patent implements separate off-chip memory space allocation for each digital signal processor through individual MMU modules. Each processor gets dedicated memory regions with isolated address translation, eliminating memory stomping risks. This segmentation approach maintains low complexity while significantly improving reliability.
3Device complexity
If program and data fetching are performed serially through a single MMU, then device complexity is reduced, but productivity deteriorates
Solution Approach 1:
The patent creates separate MMU modules for program and data ports, allowing simultaneous address translation and fetching operations. The program MMU handles instruction fetches while the data MMU handles data access, doubling the effective throughput. This segmentation directly addresses the productivity issue while maintaining manageable complexity.
Solution Approach 2:
The patent combines multiple MMU modules under a unified memory management architecture, allowing parallel operations while maintaining coordinated control. The merged structure enables both program and data fetching to proceed simultaneously through different MMU paths, resolving the serial operation bottleneck.
Data Source
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AI summary
A DSP processor, a system, and a method for accessing external memory space are disclosed. The DSP processor may include: a DSP core; and a program port and a data port which are connected to the DSP core and configured to access an external memory, where the program port and the data port are respectively configured to communicate with a memory management unit configured for management of an access address. Since the program port and the data port are respectively configured to communicate with a memory management unit for management of an access address, an operation of fetching instructions and an operation of fetching data can be carried out in parallel, thereby improving the efficiency of a DSP system.